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From: Gavin Shan <gwshan@linux.vnet.ibm.com>
To: linuxppc-dev@lists.ozlabs.org
Cc: Gavin Shan <gwshan@linux.vnet.ibm.com>
Subject: [PATCH 0/4] powerpc/powernv: Fix PE number for PF
Date: Fri, 19 Jun 2015 12:26:15 +1000
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When CONFIG_PCI_IOV is enabled in kernel configuration, the logic reserving
PEs according to consumed M64 segments in bridge's M64 window won't work
properly. The bridge's M64 window contains VF BARs, which are M64 BARs.
Current code could reserve and pick PE number according to M64 segments
accomodating VF BARs. The patches fix the issue by reserving and picking
PE numbers based on BARs (exclude VF BARs) of PCI devices, instead of
bridge's M64 window.

The code is picked from the patchset "powerpc/powernv: PCI hotplug support",
I'm working on. With the patch applied, the PE number assigned to PF is
correct:

[root@powerio-le11 ~]# lspci -vvs 0005:01:00.0
0005:01:00.0 Ethernet controller: Mellanox Technologies MT27520 Family [ConnectX-3 Pro]
	Subsystem: IBM Device 04e7
	Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- DisINTx+
	Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 0
	Interrupt: pin A routed to IRQ 510
	Region 0: Memory at 3ff200000000 (64-bit, non-prefetchable) [size=1M]
	Region 2: Memory at 3d4400000000 (64-bit, prefetchable) [size=32M]
	:

[root@powerio-le11 /]# cat /sys/bus/pci/devices/0005:01:00.0/eeh_pe_config_addr
0x40


Gavin Shan (4):
  powerpc/powernv: Allow to reserve one PE for multiple times
  powerpc/powernv: Reserve M64 PEs based on BARs
  powerpc/powernv: Boolean argument for pnv_ioda_setup_bus_PE()
  powerpc/powernv: Pick M64 PEs based on BARs

 arch/powerpc/platforms/powernv/pci-ioda.c | 127 +++++++++++-------------------
 arch/powerpc/platforms/powernv/pci.h      |   5 +-
 2 files changed, 51 insertions(+), 81 deletions(-)

-- 
2.1.0