From: Samuel Mendoza-Jonas <sam.mj@au1.ibm.com>
To: linuxppc-dev@ozlabs.org
Cc: Samuel Mendoza-Jonas <sam.mj@au1.ibm.com>,
benh@kernel.crashing.org, mpe@ellerman.id.au
Subject: [PATCH V4 1/2] powerpc/kexec: Reset secondary cpu endianess before kexec
Date: Wed, 22 Jul 2015 15:50:50 +1000 [thread overview]
Message-ID: <1437544251-19016-2-git-send-email-sam.mj@au1.ibm.com> (raw)
In-Reply-To: <1437544251-19016-1-git-send-email-sam.mj@au1.ibm.com>
If the target kernel does not inlcude the FIXUP_ENDIAN check, coming
from a different-endian kernel will cause the target kernel to panic.
All ppc64 kernels can handle starting in big-endian mode, so return to
big-endian before branching into the target kernel.
This mainly affects pseries as secondaries on powernv are returned to
OPAL.
Signed-off-by: Samuel Mendoza-Jonas <sam.mj@au1.ibm.com>
---
arch/powerpc/kernel/misc_64.S | 13 +++++++++++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/kernel/misc_64.S b/arch/powerpc/kernel/misc_64.S
index 4e314b9..6e4168c 100644
--- a/arch/powerpc/kernel/misc_64.S
+++ b/arch/powerpc/kernel/misc_64.S
@@ -475,9 +475,18 @@ _GLOBAL(kexec_wait)
#ifdef CONFIG_KEXEC /* use no memory without kexec */
lwz r4,0(r5)
cmpwi 0,r4,0
- bnea 0x60
+ beq 99b
+#ifdef CONFIG_PPC_BOOK3S_64
+ li r10,0x60
+ mfmsr r11
+ clrrdi r11,r11,1 /* Clear MSR_LE */
+ mtsrr0 r10
+ mtsrr1 r11
+ rfid
+#else
+ ba 0x60
+#endif
#endif
- b 99b
/* this can be in text because we won't change it until we are
* running in real anyways
--
2.4.6
next prev parent reply other threads:[~2015-07-22 5:51 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-07-22 5:50 [PATCH V4 0/2] powerpc/kexec: Reset endianess before kexec Samuel Mendoza-Jonas
2015-07-22 5:50 ` Samuel Mendoza-Jonas [this message]
2015-08-21 7:43 ` [V4, 1/2] powerpc/kexec: Reset secondary cpu " Michael Ellerman
2015-07-22 5:50 ` [PATCH V4 2/2] powerpc/kexec: Reset HILE before kexec_sequence Samuel Mendoza-Jonas
2015-08-21 7:43 ` [V4,2/2] " Michael Ellerman
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