* [PATCH] powerpc/fsl-pci: fix pcie range issue for some P1/P2 boards
@ 2015-07-22 10:08 Zhiqiang Hou
2015-07-25 2:48 ` Scott Wood
0 siblings, 1 reply; 5+ messages in thread
From: Zhiqiang Hou @ 2015-07-22 10:08 UTC (permalink / raw)
To: linuxppc-dev, benh, paulus, mpe; +Cc: b21284, Hou Zhiqiang
From: Hou Zhiqiang <B48286@freescale.com>
Impact board list:
P1020MBG-PC. P1022DS, P2020RDB
All above boards have its PCIE memory range less than 0xbfff_ffff,
but in dts its boundary value was 0xe0000000. Both of them was maped
to the same boundary 0xe0000000 which was Overlapped and crossed. Cpu
will access the illicit memery addr and detect error then lead to
cpu stall.
So update dts for these boards.
error log:
PCI host bridge /pcie@ffe09000 (primary) ranges:
MEM 0x00000000a0000000..0x00000000bfffffff -> 0x00000000e0000000
IO 0x00000000ffc10000..0x00000000ffc1ffff -> 0x0000000000000000
/pcie@ffe09000: PCICSRBAR @ 0xdff00000
Found FSL PCI host bridge at 0x00000000ffe0a000. Firmware bus number: 0->0
PCI host bridge /pcie@ffe0a000 ranges:
MEM 0x0000000080000000..0x000000009fffffff -> 0x00000000e0000000
IO 0x00000000ffc00000..0x00000000ffc0ffff -> 0x0000000000000000
/pcie@ffe0a000: PCICSRBAR @ 0xdff00000
.........
ata2: SATA link down (SStatus 0 SControl 300)
INFO: rcu_sched self-detected stall on CPU { 1} INFO: rcu_sched detected
stalls on CPUs/tasks: { 1} (detected by 0, t=5252 jiffies, g=4294967053,
c=4294967052, q=76)
Task dump for CPU 1:
swapper/0 R running 0 1 0 0x00000804
Call Trace:
[ee049c30] [c00091c8] timer_interrupt+0x180/0x1a0 (unreliable)
[ee049c60] [c000e7ec] ret_from_except+0x0/0x18
Signed-off-by: Hou Zhiqiang <B48286@freescale.com>
---
arch/powerpc/boot/dts/p1020mbg-pc_32b.dts | 14 +++++++-------
arch/powerpc/boot/dts/p1022ds_32b.dts | 18 +++++++++---------
arch/powerpc/boot/dts/p2020rdb-pc_32b.dts | 12 ++++++------
3 files changed, 22 insertions(+), 22 deletions(-)
diff --git a/arch/powerpc/boot/dts/p1020mbg-pc_32b.dts b/arch/powerpc/boot/dts/p1020mbg-pc_32b.dts
index ab8f076..4dfbd30 100644
--- a/arch/powerpc/boot/dts/p1020mbg-pc_32b.dts
+++ b/arch/powerpc/boot/dts/p1020mbg-pc_32b.dts
@@ -55,12 +55,12 @@
};
pci0: pcie@ffe09000 {
- reg = <0x0 0xffe09000 0x0 0x1000>;
- ranges = <0x2000000 0x0 0xe0000000 0x0 0xa0000000 0x0 0x20000000
+ ranges = <0x2000000 0x0 0xa0000000 0x0 0xa0000000 0x0 0x20000000
0x1000000 0x0 0x00000000 0x0 0xffc10000 0x0 0x10000>;
+ reg = <0x0 0xffe09000 0x0 0x1000>;
pcie@0 {
- ranges = <0x2000000 0x0 0xe0000000
- 0x2000000 0x0 0xe0000000
+ ranges = <0x2000000 0x0 0xa0000000
+ 0x2000000 0x0 0xa0000000
0x0 0x20000000
0x1000000 0x0 0x0
@@ -71,11 +71,11 @@
pci1: pcie@ffe0a000 {
reg = <0x0 0xffe0a000 0x0 0x1000>;
- ranges = <0x2000000 0x0 0xe0000000 0x0 0x80000000 0x0 0x20000000
+ ranges = <0x2000000 0x0 0x80000000 0x0 0x80000000 0x0 0x20000000
0x1000000 0x0 0x00000000 0x0 0xffc00000 0x0 0x10000>;
pcie@0 {
- ranges = <0x2000000 0x0 0xe0000000
- 0x2000000 0x0 0xe0000000
+ ranges = <0x2000000 0x0 0x80000000
+ 0x2000000 0x0 0x80000000
0x0 0x20000000
0x1000000 0x0 0x0
diff --git a/arch/powerpc/boot/dts/p1022ds_32b.dts b/arch/powerpc/boot/dts/p1022ds_32b.dts
index d96cae0..803e0db 100644
--- a/arch/powerpc/boot/dts/p1022ds_32b.dts
+++ b/arch/powerpc/boot/dts/p1022ds_32b.dts
@@ -54,12 +54,12 @@
};
pci0: pcie@ffe09000 {
- ranges = <0x2000000 0x0 0xe0000000 0 0xa0000000 0x0 0x20000000
+ ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
reg = <0x0 0xffe09000 0 0x1000>;
pcie@0 {
- ranges = <0x2000000 0x0 0xe0000000
- 0x2000000 0x0 0xe0000000
+ ranges = <0x2000000 0x0 0xa0000000
+ 0x2000000 0x0 0xa0000000
0x0 0x20000000
0x1000000 0x0 0x0
@@ -69,12 +69,12 @@
};
pci1: pcie@ffe0a000 {
- ranges = <0x2000000 0x0 0xe0000000 0 0xc0000000 0x0 0x20000000
+ ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000
0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>;
reg = <0 0xffe0a000 0 0x1000>;
pcie@0 {
- ranges = <0x2000000 0x0 0xe0000000
- 0x2000000 0x0 0xe0000000
+ ranges = <0x2000000 0x0 0xc0000000
+ 0x2000000 0x0 0xc0000000
0x0 0x20000000
0x1000000 0x0 0x0
@@ -84,12 +84,12 @@
};
pci2: pcie@ffe0b000 {
- ranges = <0x2000000 0x0 0xe0000000 0 0x80000000 0x0 0x20000000
+ ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
reg = <0 0xffe0b000 0 0x1000>;
pcie@0 {
- ranges = <0x2000000 0x0 0xe0000000
- 0x2000000 0x0 0xe0000000
+ ranges = <0x2000000 0x0 0x80000000
+ 0x2000000 0x0 0x80000000
0x0 0x20000000
0x1000000 0x0 0x0
diff --git a/arch/powerpc/boot/dts/p2020rdb-pc_32b.dts b/arch/powerpc/boot/dts/p2020rdb-pc_32b.dts
index 57573bd..1676d81 100644
--- a/arch/powerpc/boot/dts/p2020rdb-pc_32b.dts
+++ b/arch/powerpc/boot/dts/p2020rdb-pc_32b.dts
@@ -63,11 +63,11 @@
pci1: pcie@ffe09000 {
reg = <0 0xffe09000 0 0x1000>;
- ranges = <0x2000000 0x0 0xe0000000 0 0xa0000000 0x0 0x20000000
+ ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
pcie@0 {
- ranges = <0x2000000 0x0 0xe0000000
- 0x2000000 0x0 0xe0000000
+ ranges = <0x2000000 0x0 0xa0000000
+ 0x2000000 0x0 0xa0000000
0x0 0x20000000
0x1000000 0x0 0x0
@@ -78,11 +78,11 @@
pci0: pcie@ffe0a000 {
reg = <0 0xffe0a000 0 0x1000>;
- ranges = <0x2000000 0x0 0xe0000000 0 0x80000000 0x0 0x20000000
+ ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
pcie@0 {
- ranges = <0x2000000 0x0 0xe0000000
- 0x2000000 0x0 0xe0000000
+ ranges = <0x2000000 0x0 0x80000000
+ 0x2000000 0x0 0x80000000
0x0 0x20000000
0x1000000 0x0 0x0
--
2.1.0.27.g96db324
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH] powerpc/fsl-pci: fix pcie range issue for some P1/P2 boards
2015-07-22 10:08 [PATCH] powerpc/fsl-pci: fix pcie range issue for some P1/P2 boards Zhiqiang Hou
@ 2015-07-25 2:48 ` Scott Wood
2015-07-29 2:34 ` Hou Zhiqiang
0 siblings, 1 reply; 5+ messages in thread
From: Scott Wood @ 2015-07-25 2:48 UTC (permalink / raw)
To: Zhiqiang Hou; +Cc: linuxppc-dev, benh, paulus, mpe, b21284
On Wed, 2015-07-22 at 18:08 +0800, Zhiqiang Hou wrote:
> From: Hou Zhiqiang <B48286@freescale.com>
You CCed this to
b21284@freescale.com. Who is that? It would be nice to use "friendly"
e-mail addresses, but at least include the name along with the e-mail address.
I suggest CCing the people who added these device trees.
> Impact board list:
> P1020MBG-PC. P1022DS, P2020RDB
> All above boards have its PCIE memory range less than 0xbfff_ffff,
If you mean that the physical address of the memory region is <= 0xbfff_ffff,
I don't see the relevance.
> but in dts its boundary value was 0xe0000000. Both of them was maped
> to the same boundary 0xe0000000 which was Overlapped and crossed.
By "boundary" do you mean the PCIe bus address? Why is it a problem for
these independent PCIe root complexes to have the same PCIe bus addresses?
> Cpu will access the illicit memery addr and detect error then lead to
> cpu stall. So update dts for these boards.
What is illicit about it?
Why isn't the problem seen in the 36-bit device trees, which do the same
thing?
-Scott
^ permalink raw reply [flat|nested] 5+ messages in thread
* RE: [PATCH] powerpc/fsl-pci: fix pcie range issue for some P1/P2 boards
2015-07-25 2:48 ` Scott Wood
@ 2015-07-29 2:34 ` Hou Zhiqiang
2015-07-29 2:35 ` Scott Wood
0 siblings, 1 reply; 5+ messages in thread
From: Hou Zhiqiang @ 2015-07-29 2:34 UTC (permalink / raw)
To: Scott Wood
Cc: linuxppc-dev@lists.ozlabs.org, benh@kernel.crashing.org,
paulus@samba.org, mpe@ellerman.id.au, Hu Vincent
SGkgU2NvdHQgYW5kIGFsbCwNCg0KUGxlYXNlIGlnbm9yZSB0aGlzIHBhdGNoIQ0KDQo+IC0tLS0t
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aXFpYW5nDQo=
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] powerpc/fsl-pci: fix pcie range issue for some P1/P2 boards
2015-07-29 2:34 ` Hou Zhiqiang
@ 2015-07-29 2:35 ` Scott Wood
2015-07-30 10:02 ` Hou Zhiqiang
0 siblings, 1 reply; 5+ messages in thread
From: Scott Wood @ 2015-07-29 2:35 UTC (permalink / raw)
To: Hou Zhiqiang-B48286
Cc: linuxppc-dev@lists.ozlabs.org, benh@kernel.crashing.org,
paulus@samba.org, mpe@ellerman.id.au, Hu Mingkai-B21284
On Tue, 2015-07-28 at 21:34 -0500, Hou Zhiqiang-B48286 wrote:
> Hi Scott and all,
>
> Please ignore this patch!
Did you figure out what was actually causing you to see CPU stalls?
-Scott
^ permalink raw reply [flat|nested] 5+ messages in thread
* RE: [PATCH] powerpc/fsl-pci: fix pcie range issue for some P1/P2 boards
2015-07-29 2:35 ` Scott Wood
@ 2015-07-30 10:02 ` Hou Zhiqiang
0 siblings, 0 replies; 5+ messages in thread
From: Hou Zhiqiang @ 2015-07-30 10:02 UTC (permalink / raw)
To: Scott Wood
Cc: linuxppc-dev@lists.ozlabs.org, benh@kernel.crashing.org,
paulus@samba.org, mpe@ellerman.id.au, Hu Vincent
SGkgU2NvdHQsDQoNCj4gLS0tLS1PcmlnaW5hbCBNZXNzYWdlLS0tLS0NCj4gRnJvbTogV29vZCBT
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^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2015-07-30 10:03 UTC | newest]
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2015-07-22 10:08 [PATCH] powerpc/fsl-pci: fix pcie range issue for some P1/P2 boards Zhiqiang Hou
2015-07-25 2:48 ` Scott Wood
2015-07-29 2:34 ` Hou Zhiqiang
2015-07-29 2:35 ` Scott Wood
2015-07-30 10:02 ` Hou Zhiqiang
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