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Date: Thu, 6 Aug 2015 12:20:37 +0800
From: Chenhui Zhao <chenhui.zhao@freescale.com>
Subject: Re: [PATCH 1/3] Powerpc: mpc85xx: refactor the PM operations
To: Scott Wood <scottwood@freescale.com>
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On Thu, Aug 6, 2015 at 10:57 AM, Scott Wood <scottwood@freescale.com> 
wrote:
> On Wed, 2015-08-05 at 18:11 +0800, Chenhui Zhao wrote:
>>  On Tue, Aug 4, 2015 at 4:26 AM, Scott Wood <scottwood@freescale.com>
>>  wrote:
>>  > On Mon, 2015-08-03 at 19:32 +0800, Chenhui Zhao wrote:
>>  > >  >
>>  >
>>  > >  On Sat, Aug 1, 2015 at 7:59 AM, Scott Wood 
>> <scottwood@freescale.com>
>>  > >  wrote:
>>  >
>>  > >  >
>>  > >  > Could you explain irq_mask()?  Why would there still be IRQs
>>  > > destined
>>  > >  > for
>>  > >  > this CPU at this point?
>>  > >
>>  > >  This function just masks irq by setting the registers in RCPM 
>> (for
>>  > >  example, RCPM_CPMIMR, RCPM_CPMCIMR). Actually, all irqs to 
>> this CPU
>>  > >  have been migrated to other CPUs.
>>  >
>>  > So why do we need to set those bits in RCPM?  Is it just caution?
>> 
>>  Setting these bits can mask interrupts signalled to RCPM from MPIC 
>> as a
>>  means of
>>  waking up from a lower power state. So, cores will not be waked up
>>  unexpectedly.
> 
> Why would the MPIC be signalling those interrupts if they've been 
> masked at
> the MPIC?
> 
> -Scott
> 

The interrupts to RCPM from MPIC are IRQ, Machine Check, NMI and 
Critical interrupts. Some of them didn't be masked in MPIC.

-Chenhui