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Subject: Re: [PATCH v2] powerpc32: memcpy/memset: only use dcbz once cache
 is enabled
From: Scott Wood <scottwood@freescale.com>
To: Christophe Leroy <christophe.leroy@c-s.fr>
CC: Benjamin Herrenschmidt <benh@kernel.crashing.org>, Paul Mackerras
 <paulus@samba.org>, Michael Ellerman <mpe@ellerman.id.au>,
 <sojkam1@fel.cvut.cz>, <linux-kernel@vger.kernel.org>,
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Date: Thu, 10 Sep 2015 17:05:43 -0500
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On Thu, 2015-09-10 at 08:41 +0200, Christophe Leroy wrote:
>  
> +/* Cache related sections */
> +#define BEGIN_CACHE_SECTION_NESTED(label)    START_FTR_SECTION(label)
> +#define BEGIN_CACHE_SECTION                  START_FTR_SECTION(97)
> +
> +#define END_CACHE_SECTION_NESTED(msk, val, label)            \
> +     FTR_SECTION_ELSE_NESTED(label)                          \
> +     MAKE_FTR_SECTION_ENTRY(msk, val, label, __cache_fixup)
> +
> +#define END_CACHE_SECTION(msk, val)          \
> +     END_CACHE_SECTION_NESTED(msk, val, 97)
> +
> +#define END_CACHE_SECTION_IFSET(msk) END_CACHE_SECTION((msk), (msk))
> +#define END_CACHE_SECTION_IFCLR(msk) END_CACHE_SECTION((msk), 0)
> +
> +/* CACHE feature sections with alternatives, use BEGIN_FTR_SECTION to 
> start */
> +#define CACHE_SECTION_ELSE_NESTED(label)     FTR_SECTION_ELSE_NESTED(label)
> +#define CACHE_SECTION_ELSE   CACHE_SECTION_ELSE_NESTED(97)
> +#define ALT_CACHE_SECTION_END_NESTED(msk, val, label)        \
> +     MAKE_FTR_SECTION_ENTRY(msk, val, label, __cache_fixup)
> +#define ALT_CACHE_SECTION_END_NESTED_IFSET(msk, label)       \
> +     ALT_CACHE_SECTION_END_NESTED(msk, msk, label)
> +#define ALT_CACHE_SECTION_END_NESTED_IFCLR(msk, label)       \
> +     ALT_CACHE_SECTION_END_NESTED(msk, 0, label)
> +#define ALT_CACHE_SECTION_END(msk, val)      \
> +     ALT_CACHE_SECTION_END_NESTED(msk, val, 97)
> +#define ALT_CACHE_SECTION_END_IFSET(msk)     \
> +     ALT_CACHE_SECTION_END_NESTED_IFSET(msk, 97)
> +#define ALT_CACHE_SECTION_END_IFCLR(msk)     \
> +     ALT_CACHE_SECTION_END_NESTED_IFCLR(msk, 97)

I don't think this duplication is what Michael meant by "the normal cpu 
feature sections".  What else is going to use this very specific 
infrastructure?

-Scott