From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from e23smtp04.au.ibm.com (e23smtp04.au.ibm.com [202.81.31.146]) (using TLSv1 with cipher CAMELLIA256-SHA (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 4E7A71A0635 for ; Wed, 30 Sep 2015 12:29:14 +1000 (AEST) Received: from /spool/local by e23smtp04.au.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Wed, 30 Sep 2015 12:29:12 +1000 Received: from d23relay06.au.ibm.com (d23relay06.au.ibm.com [9.185.63.219]) by d23dlp01.au.ibm.com (Postfix) with ESMTP id B10112CE8050 for ; Wed, 30 Sep 2015 12:29:10 +1000 (EST) Received: from d23av02.au.ibm.com (d23av02.au.ibm.com [9.190.235.138]) by d23relay06.au.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id t8U2SwU337683296 for ; Wed, 30 Sep 2015 12:29:06 +1000 Received: from d23av02.au.ibm.com (localhost [127.0.0.1]) by d23av02.au.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id t8U2Sbi8008578 for ; Wed, 30 Sep 2015 12:28:38 +1000 From: "Aneesh Kumar K.V" To: benh@kernel.crashing.org, paulus@samba.org, mpe@ellerman.id.au Cc: linuxppc-dev@lists.ozlabs.org, "Aneesh Kumar K.V" Subject: [PATCH V2 18/31] powerpc/mm: Increase the pte frag size. Date: Wed, 30 Sep 2015 07:57:11 +0530 Message-Id: <1443580044-30659-19-git-send-email-aneesh.kumar@linux.vnet.ibm.com> In-Reply-To: <1443580044-30659-1-git-send-email-aneesh.kumar@linux.vnet.ibm.com> References: <1443580044-30659-1-git-send-email-aneesh.kumar@linux.vnet.ibm.com> List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , We will use the increased size to store more information of 4K pte when using 64K page size. The idea is to free up bits in pte_t. Signed-off-by: Aneesh Kumar K.V --- arch/powerpc/include/asm/pgalloc-64.h | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/powerpc/include/asm/pgalloc-64.h b/arch/powerpc/include/asm/pgalloc-64.h index d8cde71f6734..4f1cc6c46728 100644 --- a/arch/powerpc/include/asm/pgalloc-64.h +++ b/arch/powerpc/include/asm/pgalloc-64.h @@ -164,15 +164,15 @@ static inline void __pte_free_tlb(struct mmu_gather *tlb, pgtable_t table, #else /* if CONFIG_PPC_64K_PAGES */ /* - * we support 16 fragments per PTE page. + * we support 8 fragments per PTE page. */ -#define PTE_FRAG_NR 16 +#define PTE_FRAG_NR 8 /* - * We use a 2K PTE page fragment and another 2K for storing - * real_pte_t hash index + * We use a 2K PTE page fragment and another 4K for storing + * real_pte_t hash index. Rounding the entire thing to 8K */ -#define PTE_FRAG_SIZE_SHIFT 12 -#define PTE_FRAG_SIZE (2 * PTRS_PER_PTE * sizeof(pte_t)) +#define PTE_FRAG_SIZE_SHIFT 13 +#define PTE_FRAG_SIZE (1UL << PTE_FRAG_SIZE_SHIFT) extern pte_t *page_table_alloc(struct mm_struct *, unsigned long, int); extern void page_table_free(struct mm_struct *, unsigned long *, int); -- 2.5.0