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From: Michael Ellerman <mpe@ellerman.id.au>
To: paulmck@linux.vnet.ibm.com, Peter Zijlstra <peterz@infradead.org>
Cc: Boqun Feng <boqun.feng@gmail.com>,
	linux-kernel@vger.kernel.org, linuxppc-dev@lists.ozlabs.org,
	Ingo Molnar <mingo@kernel.org>,
	Benjamin Herrenschmidt <benh@kernel.crashing.org>,
	Paul Mackerras <paulus@samba.org>,
	Thomas Gleixner <tglx@linutronix.de>,
	Will Deacon <will.deacon@arm.com>,
	Waiman Long <waiman.long@hp.com>,
	Davidlohr Bueso <dave@stgolabs.net>,
	 stable@vger.kernel.org
Subject: Re: [PATCH tip/locking/core v4 1/6] powerpc: atomic: Make *xchg and *cmpxchg a full barrier
Date: Mon, 26 Oct 2015 11:20:01 +0900	[thread overview]
Message-ID: <1445826001.27249.2.camel@ellerman.id.au> (raw)
In-Reply-To: <20151021193638.GU5105@linux.vnet.ibm.com>

On Wed, 2015-10-21 at 12:36 -0700, Paul E. McKenney wrote:

> On Wed, Oct 21, 2015 at 10:18:33AM +0200, Peter Zijlstra wrote:

> > On Tue, Oct 20, 2015 at 02:28:35PM -0700, Paul E. McKenney wrote:

> > > I am not seeing a sync there, but I really have to defer to the
> > > maintainers on this one.  I could easily have missed one.
> > 
> > So x86 implies a full barrier for everything that changes the CPL; and
> > some form of implied ordering seems a must if you change the privilege
> > level unless you tag every single load/store with the priv level at that
> > time, which seems the more expensive option.
> 
> And it is entirely possible that there is some similar operation
> somewhere in the powerpc entry/exit code.  I would not trust myself
> to recognize it, though.

> > So I suspect the typical implementation will flush all load/stores,
> > change the effective priv level and continue.
> > 
> > This can of course be implemented at a pure per CPU ordering (RCpc),
> > which would be in line with the rest of Power, in which case you do
> > indeed need an explicit sync to make it visible to other CPUs.
> > 
> > But yes, if Michael or Ben could clarify this it would be good.
> 
> :-) ;-) ;-)

Sorry guys, these threads are so long I tend not to read them very actively :}

Looking at the system call path, the straight line path does not include any
barriers. I can't see any hidden in macros either.

We also have an explicit sync in the switch_to() path, which suggests that we
know system call is not a full barrier.

Also looking at the architecture, section 1.5 which talks about the
synchronisation that occurs on system calls, defines nothing in terms of
memory ordering, and includes a programming note which says "Unlike the
Synchronize instruction, a context synchronizing operation does not affect the
order in which storage accesses are performed.".

Whether that's actually how it's implemented I don't know, I'll see if I can
find out.

cheers

  parent reply	other threads:[~2015-10-26  2:20 UTC|newest]

Thread overview: 43+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-10-14 15:55 [PATCH tip/locking/core v4 0/6] atomics: powerpc: Implement relaxed/acquire/release variants of some atomics Boqun Feng
2015-10-14 15:55 ` [PATCH tip/locking/core v4 1/6] powerpc: atomic: Make *xchg and *cmpxchg a full barrier Boqun Feng
2015-10-14 20:19   ` Paul E. McKenney
2015-10-14 21:04     ` Peter Zijlstra
2015-10-14 21:44       ` Paul E. McKenney
2015-10-15  0:53         ` Boqun Feng
2015-10-15  1:22           ` Boqun Feng
2015-10-15  3:07             ` Paul E. McKenney
2015-10-15  3:07           ` Paul E. McKenney
2015-10-15  4:48             ` Boqun Feng
2015-10-15 16:30               ` Paul E. McKenney
2015-10-19  0:19                 ` Boqun Feng
2015-10-15  3:11           ` Boqun Feng
2015-10-15  3:33             ` Paul E. McKenney
2015-10-15 10:35         ` Will Deacon
2015-10-15 14:40           ` Boqun Feng
2015-10-15 14:50           ` Will Deacon
2015-10-15 16:29             ` Paul E. McKenney
2015-10-15 15:42           ` Paul E. McKenney
2015-10-15 14:49     ` Boqun Feng
2015-10-15 16:16       ` Paul E. McKenney
2015-10-20  7:15     ` Boqun Feng
2015-10-20  9:21       ` Peter Zijlstra
2015-10-20 21:28         ` Paul E. McKenney
2015-10-21  8:18           ` Peter Zijlstra
2015-10-21 19:36             ` Paul E. McKenney
2015-10-26  2:06               ` Boqun Feng
2015-10-26  2:20               ` Michael Ellerman [this message]
2015-10-26  8:55                 ` Boqun Feng
2015-10-26  3:20             ` Paul Mackerras
2015-10-26  8:58               ` Boqun Feng
2015-10-21  8:45           ` Boqun Feng
2015-10-21 19:35             ` Paul E. McKenney
2015-10-21 19:48               ` Peter Zijlstra
2015-10-22 12:07                 ` Boqun Feng
2015-10-24 10:26                   ` Peter Zijlstra
2015-10-24 11:53                     ` Boqun Feng
2015-10-25 13:14                       ` Boqun Feng
2015-10-14 15:55 ` [PATCH tip/locking/core v4 2/6] atomics: Add test for atomic operations with _relaxed variants Boqun Feng
2015-10-14 15:55 ` [PATCH tip/locking/core v4 3/6] atomics: Allow architectures to define their own __atomic_op_* helpers Boqun Feng
2015-10-14 15:55 ` [PATCH tip/locking/core v4 4/6] powerpc: atomic: Implement atomic{, 64}_*_return_* variants Boqun Feng
2015-10-14 15:56 ` [PATCH tip/locking/core v4 5/6] powerpc: atomic: Implement xchg_* and atomic{, 64}_xchg_* variants Boqun Feng
2015-10-14 15:56 ` [PATCH tip/locking/core v4 6/6] powerpc: atomic: Implement cmpxchg{, 64}_* and atomic{, 64}_cmpxchg_* variants Boqun Feng

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