From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from e23smtp01.au.ibm.com (e23smtp01.au.ibm.com [202.81.31.143]) (using TLSv1 with cipher CAMELLIA256-SHA (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 321FC1A1B24 for ; Mon, 23 Nov 2015 21:35:07 +1100 (AEDT) Received: from localhost by e23smtp01.au.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Mon, 23 Nov 2015 20:35:06 +1000 Received: from d23relay07.au.ibm.com (d23relay07.au.ibm.com [9.190.26.37]) by d23dlp03.au.ibm.com (Postfix) with ESMTP id 0D2253578054 for ; Mon, 23 Nov 2015 21:35:04 +1100 (EST) Received: from d23av04.au.ibm.com (d23av04.au.ibm.com [9.190.235.139]) by d23relay07.au.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id tANAYv7c36110454 for ; Mon, 23 Nov 2015 21:35:05 +1100 Received: from d23av04.au.ibm.com (localhost [127.0.0.1]) by d23av04.au.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id tANAYUvK028272 for ; Mon, 23 Nov 2015 21:34:31 +1100 From: "Aneesh Kumar K.V" To: benh@kernel.crashing.org, paulus@samba.org, mpe@ellerman.id.au, Scott Wood , Denis Kirjanov Cc: linuxppc-dev@lists.ozlabs.org, "Aneesh Kumar K.V" Subject: [PATCH V2 07/10] powerpc/mm: update PTE frag size Date: Mon, 23 Nov 2015 16:03:42 +0530 Message-Id: <1448274825-30289-8-git-send-email-aneesh.kumar@linux.vnet.ibm.com> In-Reply-To: <1448274825-30289-1-git-send-email-aneesh.kumar@linux.vnet.ibm.com> References: <1448274825-30289-1-git-send-email-aneesh.kumar@linux.vnet.ibm.com> List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Now that we don't track 4k subpage information we can use 2K PTE fragments. Signed-off-by: Aneesh Kumar K.V --- arch/powerpc/include/asm/book3s/64/hash-64k.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/powerpc/include/asm/book3s/64/hash-64k.h b/arch/powerpc/include/asm/book3s/64/hash-64k.h index 5062c6d423fd..a28dbfe2baed 100644 --- a/arch/powerpc/include/asm/book3s/64/hash-64k.h +++ b/arch/powerpc/include/asm/book3s/64/hash-64k.h @@ -39,14 +39,14 @@ */ #define PTE_RPN_SHIFT (30) /* - * we support 8 fragments per PTE page of 64K size. + * we support 32 fragments per PTE page of 64K size. */ -#define PTE_FRAG_NR 8 +#define PTE_FRAG_NR 32 /* * We use a 2K PTE page fragment and another 4K for storing * real_pte_t hash index. Rounding the entire thing to 8K */ -#define PTE_FRAG_SIZE_SHIFT 13 +#define PTE_FRAG_SIZE_SHIFT 11 #define PTE_FRAG_SIZE (1UL << PTE_FRAG_SIZE_SHIFT) /* -- 2.5.0