From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from host.buserror.net (host.buserror.net [209.198.135.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 5F4DC1A034B for ; Thu, 4 Feb 2016 10:03:24 +1100 (AEDT) Message-ID: <1454540598.2486.22.camel@buserror.net> From: Scott Wood To: Edward L Swarthout , Zhiqiang Hou , "linuxppc-dev@lists.ozlabs.org" , "mpe@ellerman.id.au" Cc: "Mingkai.Hu@freescale.com" Date: Wed, 03 Feb 2016 17:03:18 -0600 In-Reply-To: References: <1451893517-20934-1-git-send-email-Zhiqiang.Hou@freescale.com> ,<1454299649.2486.11.camel@buserror.net> Content-Type: text/plain; charset="UTF-8" Mime-Version: 1.0 Subject: Re: [PATCH] powerpc/fsl-pci: Correct the comparison of the LTSSM List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , On Wed, 2016-02-03 at 21:32 +0000, Edward L Swarthout wrote: > From: Scott Wood: > > On Mon, 2016-02-01 at 03:57 +0000, Zhiqiang Hou wrote: > > > Any comments? > > > > Only that it was submitted too late for the last merge window, and I have > > not > > yet begun processing patches for the next one. If you meant this to be a > > fix > > important enough to go in outside the merge window, it's missing any > > statement > > of what the actual symptoms are. > > > > > -----Original Message----- > > > From: Zhiqiang Hou [mailto:Zhiqiang.Hou@freescale.com] > > > To: linuxppc-dev@lists.ozlabs.org; benh@kernel.crashing.org; > > > Subject: [PATCH] powerpc/fsl-pci: Correct the comparison of the LTSSM > > > > > > Only the value PCIE_LTSSM_L0 stands for the link is up, instead of >= > > > PCIE_LTSSM_L0. > > > > > > diff --git a/arch/powerpc/sysdev/fsl_pci.c > > > b/arch/powerpc/sysdev/fsl_pci.c > > > @@ -73,7 +73,7 @@ static int fsl_pcie_check_link(struct pci_controller > > > early_read_config_dword(hose, 0, 0, PCIE_LTSSM, > > > - if (val < PCIE_LTSSM_L0) > > > + if (val != PCIE_LTSSM_L0) > > > return 1; > > This patch is incorrect as there are actually two states L0 and L0s > (standby) > that indicate an active link (a LTSSM value of 0x11 or 0x12). > > The next user manual revision should contain this detail. The next manual of what chip? Are there any non-active states for which the current test does not work? -Scott