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Message-ID: <1456335458.3941.3.camel@neuling.org>
Subject: Re: [PATCH] cxl: Fix PSL timebase synchronization detection
From: Michael Neuling <mikey@neuling.org>
To: Frederic Barrat <fbarrat@linux.vnet.ibm.com>, ian@ozlabs.au.ibm.com,
 linuxppc-dev@lists.ozlabs.org
Date: Wed, 24 Feb 2016 11:37:38 -0600
In-Reply-To: <1456334871-30397-1-git-send-email-fbarrat@linux.vnet.ibm.com>
References: <1456334871-30397-1-git-send-email-fbarrat@linux.vnet.ibm.com>
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On Wed, 2016-02-24 at 18:27 +0100, Frederic Barrat wrote:
> The PSL timebase synchronization is seemingly failing for
> configuration not including VIRT_CPU_ACCOUNTING_NATIVE. The driver
> shows the following trace in dmesg:
> PSL: Timebase sync: giving up!
>=20
> The PSL timebase register is actually syncing correctly, but the cxl
> driver is not detecting it. Fix is to use the proper timebase-to-time
> conversion.
>=20
> Signed-off-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com>

Looks good!

Acked-by: Michael Neuling <mikey@neuling.org>


> Cc: <stable@vger.kernel.org> # 4.3+
> ---
>  drivers/misc/cxl/pci.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>=20
> diff --git a/drivers/misc/cxl/pci.c b/drivers/misc/cxl/pci.c
> index 4c1903f..0c6c17a1 100644
> --- a/drivers/misc/cxl/pci.c
> +++ b/drivers/misc/cxl/pci.c
> @@ -415,7 +415,7 @@ static int cxl_setup_psl_timebase(struct cxl
> *adapter, struct pci_dev *dev)
>  		delta =3D mftb() - psl_tb;
>  		if (delta < 0)
>  			delta =3D -delta;
> -	} while (cputime_to_usecs(delta) > 16);
> +	} while (tb_to_ns(delta) > 16000);
> =20
>  	return 0;
>  }