From: "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com>
To: benh@kernel.crashing.org, paulus@samba.org, mpe@ellerman.id.au
Cc: linuxppc-dev@lists.ozlabs.org,
"Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com>
Subject: [PATCH 06/14] powerpc/mm: Remove RPN_SHIFT and RPN_SIZE
Date: Mon, 7 Mar 2016 19:09:26 +0530 [thread overview]
Message-ID: <1457357974-20839-6-git-send-email-aneesh.kumar@linux.vnet.ibm.com> (raw)
In-Reply-To: <1457357974-20839-1-git-send-email-aneesh.kumar@linux.vnet.ibm.com>
We had them as page size dependent. Use PAGE_SIZE instead. While there
remove them and define RPN_MASK better.
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
---
arch/powerpc/include/asm/book3s/64/hash-4k.h | 4 ----
arch/powerpc/include/asm/book3s/64/hash-64k.h | 11 +----------
arch/powerpc/include/asm/book3s/64/hash.h | 10 +++++-----
arch/powerpc/include/asm/book3s/64/pgtable.h | 4 ++--
arch/powerpc/mm/pgtable_64.c | 2 +-
5 files changed, 9 insertions(+), 22 deletions(-)
diff --git a/arch/powerpc/include/asm/book3s/64/hash-4k.h b/arch/powerpc/include/asm/book3s/64/hash-4k.h
index 5f08a0832238..772850e517f3 100644
--- a/arch/powerpc/include/asm/book3s/64/hash-4k.h
+++ b/arch/powerpc/include/asm/book3s/64/hash-4k.h
@@ -51,10 +51,6 @@
#define _PAGE_HPTEFLAGS (_PAGE_BUSY | _PAGE_HASHPTE | \
_PAGE_F_SECOND | _PAGE_F_GIX)
-/* shift to put page number into pte */
-#define PTE_RPN_SHIFT (12)
-#define PTE_RPN_SIZE (45) /* gives 57-bit real addresses */
-
#define _PAGE_4K_PFN 0
#ifndef __ASSEMBLY__
/*
diff --git a/arch/powerpc/include/asm/book3s/64/hash-64k.h b/arch/powerpc/include/asm/book3s/64/hash-64k.h
index 279ded72f1db..a053e8a1d0d1 100644
--- a/arch/powerpc/include/asm/book3s/64/hash-64k.h
+++ b/arch/powerpc/include/asm/book3s/64/hash-64k.h
@@ -40,15 +40,6 @@
/* PTE flags to conserve for HPTE identification */
#define _PAGE_HPTEFLAGS (_PAGE_BUSY | _PAGE_F_SECOND | \
_PAGE_F_GIX | _PAGE_HASHPTE | _PAGE_COMBO)
-
-/* Shift to put page number into pte.
- *
- * That gives us a max RPN of 41 bits, which means a max of 57 bits
- * of addressable physical space, or 53 bits for the special 4k PFNs.
- */
-#define PTE_RPN_SHIFT (16)
-#define PTE_RPN_SIZE (41)
-
/*
* we support 16 fragments per PTE page of 64K size.
*/
@@ -125,7 +116,7 @@ extern bool __rpte_sub_valid(real_pte_t rpte, unsigned long index);
(((pte) & _PAGE_COMBO)? MMU_PAGE_4K: MMU_PAGE_64K)
#define remap_4k_pfn(vma, addr, pfn, prot) \
- (WARN_ON(((pfn) >= (1UL << PTE_RPN_SIZE))) ? -EINVAL : \
+ (WARN_ON(((pfn) > (PTE_RPN_MASK >> PAGE_SHIFT))) ? -EINVAL : \
remap_pfn_range((vma), (addr), (pfn), PAGE_SIZE, \
__pgprot(pgprot_val((prot)) | _PAGE_4K_PFN)))
diff --git a/arch/powerpc/include/asm/book3s/64/hash.h b/arch/powerpc/include/asm/book3s/64/hash.h
index fbefbaa92736..8ccb2970f30f 100644
--- a/arch/powerpc/include/asm/book3s/64/hash.h
+++ b/arch/powerpc/include/asm/book3s/64/hash.h
@@ -136,10 +136,10 @@
#define PTE_ATOMIC_UPDATES 1
#define _PTE_NONE_MASK _PAGE_HPTEFLAGS
/*
- * The mask convered by the RPN must be a ULL on 32-bit platforms with
- * 64-bit PTEs
+ * We support 57 bit real address in pte. Clear everything above 57, and
+ * every thing below PAGE_SHIFT;
*/
-#define PTE_RPN_MASK (((1UL << PTE_RPN_SIZE) - 1) << PTE_RPN_SHIFT)
+#define PTE_RPN_MASK (((1UL << 57) - 1) & (PAGE_MASK))
/*
* _PAGE_CHG_MASK masks of bits that are to be preserved across
* pgprot changes
@@ -439,13 +439,13 @@ static inline int pte_present(pte_t pte)
*/
static inline pte_t pfn_pte(unsigned long pfn, pgprot_t pgprot)
{
- return __pte((((pte_basic_t)(pfn) << PTE_RPN_SHIFT) & PTE_RPN_MASK) |
+ return __pte((((pte_basic_t)(pfn) << PAGE_SHIFT) & PTE_RPN_MASK) |
pgprot_val(pgprot));
}
static inline unsigned long pte_pfn(pte_t pte)
{
- return (pte_val(pte) & PTE_RPN_MASK) >> PTE_RPN_SHIFT;
+ return (pte_val(pte) & PTE_RPN_MASK) >> PAGE_SHIFT;
}
/* Generic modifiers for PTE bits */
diff --git a/arch/powerpc/include/asm/book3s/64/pgtable.h b/arch/powerpc/include/asm/book3s/64/pgtable.h
index 97d06de8dbf6..144680382306 100644
--- a/arch/powerpc/include/asm/book3s/64/pgtable.h
+++ b/arch/powerpc/include/asm/book3s/64/pgtable.h
@@ -172,10 +172,10 @@ extern struct page *pgd_page(pgd_t pgd);
#define SWP_TYPE_BITS 5
#define __swp_type(x) (((x).val >> _PAGE_BIT_SWAP_TYPE) \
& ((1UL << SWP_TYPE_BITS) - 1))
-#define __swp_offset(x) (((x).val & PTE_RPN_MASK) >> PTE_RPN_SHIFT)
+#define __swp_offset(x) (((x).val & PTE_RPN_MASK) >> PAGE_SHIFT)
#define __swp_entry(type, offset) ((swp_entry_t) { \
((type) << _PAGE_BIT_SWAP_TYPE) \
- | (((offset) << PTE_RPN_SHIFT) & PTE_RPN_MASK)})
+ | (((offset) << PAGE_SHIFT) & PTE_RPN_MASK)})
/*
* swp_entry_t must be independent of pte bits. We build a swp_entry_t from
* swap type and offset we get from swap and convert that to pte to find a
diff --git a/arch/powerpc/mm/pgtable_64.c b/arch/powerpc/mm/pgtable_64.c
index 441905f7bba4..1254cf107871 100644
--- a/arch/powerpc/mm/pgtable_64.c
+++ b/arch/powerpc/mm/pgtable_64.c
@@ -762,7 +762,7 @@ pmd_t pfn_pmd(unsigned long pfn, pgprot_t pgprot)
{
unsigned long pmdv;
- pmdv = (pfn << PTE_RPN_SHIFT) & PTE_RPN_MASK;
+ pmdv = (pfn << PAGE_SHIFT) & PTE_RPN_MASK;
return pmd_set_protbits(__pmd(pmdv), pgprot);
}
--
2.5.0
next prev parent reply other threads:[~2016-03-07 13:40 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-03-07 13:39 [PATCH 01/14] powerpc/mm: Use big endian page table for book3s 64 Aneesh Kumar K.V
2016-03-07 13:39 ` [PATCH 02/14] powerpc/mm: use _PAGE_READ to indicate Read access Aneesh Kumar K.V
2016-03-07 13:39 ` [PATCH 03/14] powerpc/mm/subpage: Clear RWX bit to indicate no access Aneesh Kumar K.V
2016-03-07 13:39 ` [PATCH 04/14] powerpc/mm: Use pte_user instead of opencoding Aneesh Kumar K.V
2016-03-07 13:39 ` [PATCH 05/14] powerpc/mm: Replace _PAGE_USER with _PAGE_PRIVILEGED Aneesh Kumar K.V
2016-03-22 6:05 ` Michael Neuling
2016-03-26 5:32 ` Aneesh Kumar K.V
2016-03-07 13:39 ` Aneesh Kumar K.V [this message]
2016-03-07 13:39 ` [PATCH 07/14] powerpc/mm: Update _PAGE_KERNEL_RO Aneesh Kumar K.V
2016-03-07 13:39 ` [PATCH 08/14] powerpc/mm: Use helper for finding pte bits mapping I/O area Aneesh Kumar K.V
2016-03-07 13:39 ` [PATCH 09/14] powerpc/mm: Drop WIMG in favour of new constants Aneesh Kumar K.V
2016-03-07 17:29 ` kbuild test robot
2016-03-22 4:59 ` Michael Neuling
2016-03-26 6:12 ` Aneesh Kumar K.V
2016-03-07 13:39 ` [PATCH 10/14] powerpc/mm: Use generic version of pmdp_clear_flush_young Aneesh Kumar K.V
2016-03-07 13:39 ` [PATCH 11/14] powerpc/mm: Use generic version of ptep_clear_flush_young Aneesh Kumar K.V
2016-03-07 13:39 ` [PATCH 12/14] powerpc/mm: Move common data structure between radix and hash to book3s 64 generic headers Aneesh Kumar K.V
2016-03-07 13:39 ` [PATCH 13/14] powerpc/mm/power9: Add partition table format Aneesh Kumar K.V
2016-03-07 13:39 ` [PATCH 14/14] powerpc/mm/hash: Add support for POWER9 hash Aneesh Kumar K.V
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