From: Michael Neuling <mikey@neuling.org>
To: Philippe Bergheaud <felix@linux.vnet.ibm.com>
Cc: linuxppc-dev@lists.ozlabs.org, imunsie@au1.ibm.com
Subject: Re: [PATCH] cxl: Configure the PSL for dual port CAPI on Naples
Date: Wed, 16 Mar 2016 19:55:10 +1100 [thread overview]
Message-ID: <1458118510.6606.7.camel@neuling.org> (raw)
In-Reply-To: <56E91E2D.60004@linux.vnet.ibm.com>
> > > + psl_dsnctl |=3D (phb_index << (63-11));
> >=20
> >=20
> > Looking at the psl docs, cappunitid in the dsndctl is bits 6 to 13.
> > So
> > why 11 here?
> >=20
> Because on POWER8NVL, dsndctl bit 11 =3D=3D phb_index =3D=3D cappunitid.
> Bits 6-10 and 12-13 do not change between POWER8 and POWER8NVL.
OK, can you document that better as what you're doing now is not clear
even when reading the associated docs.
Mikey
prev parent reply other threads:[~2016-03-16 8:55 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-03-15 14:26 [PATCH] cxl: Configure the PSL for dual port CAPI on Naples Philippe Bergheaud
2016-03-16 1:15 ` Michael Neuling
2016-03-16 8:49 ` Philippe Bergheaud
2016-03-16 8:55 ` Michael Neuling [this message]
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