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From: Ian Munsie <imunsie@au1.ibm.com>
To: "andrew.donnellan" <andrew.donnellan@au1.ibm.com>
Cc: linuxppc-dev <linuxppc-dev@lists.ozlabs.org>
Subject: Re: [PATCH] cxl: fix setting of _PAGE_USER bit when handling page faults
Date: Fri, 18 Mar 2016 17:30:23 +1100	[thread overview]
Message-ID: <1458282296-sup-2460@x230.ozlabs.ibm.com> (raw)
In-Reply-To: <1458273681-18588-1-git-send-email-andrew.donnellan@au1.ibm.com>

Excerpts from andrew.donnellan's message of 2016-03-18 15:01:21 +1100:
> Fixes: f204e0b8cedd ("cxl: Driver code for powernv PCIe based cards for
> userspace access")

It doesn't fix that since there was no cxl kernel API support at the
time, so this wasn't a regression - just something we missed when the
kernel api was added (I believe the broken test in the code was a left
over from some early bringup work and would never have been exercised on
an upstream kernel until then).

> Currently, this should only affect cxlflash.

We haven't run into any problems because of this that I am aware of - do
we have a test case for this?

> -    if ((!ctx->kernel) || ~(dar & (1ULL << 63)))
> +    if ((!ctx->kernel) || !(dar & (1ULL << 63)))

Should it be the top two bits?

-Ian

  reply	other threads:[~2016-03-18  6:57 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-03-18  4:01 [PATCH] cxl: fix setting of _PAGE_USER bit when handling page faults Andrew Donnellan
2016-03-18  6:30 ` Ian Munsie [this message]
2016-03-21  4:38   ` Andrew Donnellan
2016-03-25 10:01 ` Michael Ellerman
2016-03-25 17:15   ` Ian Munsie
2016-03-28 13:42   ` Aneesh Kumar K.V
2016-03-28 18:00     ` Aneesh Kumar K.V
2016-04-11  4:10     ` Andrew Donnellan
2016-04-11  4:27       ` Michael Ellerman
2016-04-11  4:31         ` Aneesh Kumar K.V
2016-04-11 11:14           ` Michael Ellerman
2016-04-11 13:42             ` Aneesh Kumar K.V
2016-04-12 11:42               ` Michael Ellerman
2016-03-29 22:08 ` [PATCH] " Matthew R. Ochs

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