From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from e06smtp11.uk.ibm.com (e06smtp11.uk.ibm.com [195.75.94.107]) (using TLSv1.2 with cipher CAMELLIA256-SHA (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3qTq9P6rzszDq71 for ; Tue, 22 Mar 2016 21:45:45 +1100 (AEDT) Received: from localhost by e06smtp11.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Tue, 22 Mar 2016 10:45:39 -0000 Received: from b06cxnps3074.portsmouth.uk.ibm.com (d06relay09.portsmouth.uk.ibm.com [9.149.109.194]) by d06dlp01.portsmouth.uk.ibm.com (Postfix) with ESMTP id 2F19917D8042 for ; Tue, 22 Mar 2016 10:46:09 +0000 (GMT) Received: from d06av01.portsmouth.uk.ibm.com (d06av01.portsmouth.uk.ibm.com [9.149.37.212]) by b06cxnps3074.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id u2MAjYPm8520134 for ; Tue, 22 Mar 2016 10:45:34 GMT Received: from d06av01.portsmouth.uk.ibm.com (localhost [127.0.0.1]) by d06av01.portsmouth.uk.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id u2MAjYxG011097 for ; Tue, 22 Mar 2016 04:45:34 -0600 From: Philippe Bergheaud To: linuxppc-dev@lists.ozlabs.org Cc: stewart@linux.vnet.ibm.com, imunsie@au1.ibm.com, mikey@neuling.org, Vaibhav Jain Subject: [PATCH] Added a 5ms wait after a msi-irq is masked Date: Tue, 22 Mar 2016 11:45:54 +0100 Message-Id: <1458643554-22766-1-git-send-email-felix@linux.vnet.ibm.com> List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , From: Vaibhav Jain Adds a 5ms wait to phb3_msi_set_xive after the interrupt is masked so that the kernel delays cleanup until an irq if its in-flight is handled. The value 5ms is the worst case time needed by an irq to be presented to the host after its generated. Signed-off-by: Vaibhav Jain --- This patch requires the following patches: https://patchwork.ozlabs.org/patch/581764/ https://patchwork.ozlabs.org/patch/581765/ hw/phb3.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/hw/phb3.c b/hw/phb3.c index fbdcb9e..e5d49b2 100644 --- a/hw/phb3.c +++ b/hw/phb3.c @@ -1751,6 +1751,8 @@ static int64_t phb3_msi_set_xive(void *data, PHB_IVC_UPDATE_ENABLE_Q | PHB_IVC_UPDATE_ENABLE_GEN; out_be64(p->regs + PHB_IVC_UPDATE, ivc); + /* wait for 5ms before signalling the interrupt is masked */ + time_wait_ms(5); } return OPAL_SUCCESS; -- 2.7.1