From: Jack Miller <jack@codezen.org>
To: linuxppc-dev@lists.ozlabs.org
Cc: michaele@au1.ibm.com, michael.neuling@au1.ibm.com
Subject: [RFC] P9 ldmx support
Date: Mon, 11 Apr 2016 13:57:42 -0500 [thread overview]
Message-ID: <1460401065-10540-1-git-send-email-jack@codezen.org> (raw)
All -
These are patches based on next to support the forthcoming ldmx instruction
through the existing P8 EBB infrastructure. Obviously it doesn't actually
*work* without some other patches and a P9 system, but with the context
switch change to FSCR it makes sense to get this upstream for testing ASAP.
The first patch context switches FSCR per thread so that the second patch can
lazily enable this feature (FSCR.LM) with a facility unavailable exception
and context switch two new ldmx registers (LMRR / LMSER) per thread as well.
Third patch is a couple of basic tests.
Any comments welcome.
- Jack
next reply other threads:[~2016-04-11 18:59 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-04-11 18:57 Jack Miller [this message]
2016-04-11 18:57 ` [PATCH 1/3] powerpc: Complete FSCR context switch Jack Miller
2016-04-12 23:42 ` [1/3] " Michael Ellerman
2016-04-13 10:51 ` [PATCH 1/3] " Anton Blanchard
2016-04-13 17:52 ` Jack Miller
2016-04-13 23:49 ` Michael Neuling
2016-04-14 18:39 ` Jack Miller
2016-04-14 23:11 ` Michael Neuling
2016-04-11 18:57 ` [PATCH 2/3] powerpc: Load Monitor Register Support Jack Miller
2016-04-12 5:40 ` Segher Boessenkool
2016-04-13 17:39 ` Jack Miller
2016-04-11 18:57 ` [PATCH 3/3] powerpc: Load Monitor Register Tests Jack Miller
2016-04-15 10:34 ` Madhavan Srinivasan
2016-04-12 1:05 ` [RFC] P9 ldmx support Michael Neuling
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