From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 409Vr52c4vzDqqH for ; Tue, 27 Mar 2018 23:36:37 +1100 (AEDT) Received: from ozlabs.org (ozlabs.org [IPv6:2401:3900:2:1::2]) by bilbo.ozlabs.org (Postfix) with ESMTP id 409Vr42CFPz8vnZ for ; Tue, 27 Mar 2018 23:36:36 +1100 (AEDT) Received: from sonic306-2.consmr.mail.bf2.yahoo.com (sonic306-2.consmr.mail.bf2.yahoo.com [74.6.132.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 409Vr26pKgz9s1R for ; Tue, 27 Mar 2018 23:36:34 +1100 (AEDT) Date: Tue, 27 Mar 2018 12:36:28 +0000 (UTC) From: T T To: linuxppc-dev@ozlabs.org, Michael Ellerman Cc: mauricfo@linux.vnet.ibm.com Message-ID: <1464025410.301444.1522154188153@mail.yahoo.com> In-Reply-To: <20180327120153.31612-10-mpe@ellerman.id.au> References: <20180327120153.31612-1-mpe@ellerman.id.au> <20180327120153.31612-10-mpe@ellerman.id.au> Subject: Re: [PATCH v2 10/10] powerpc/64s: Wire up cpu_show_spectre_v2() MIME-Version: 1.0 Content-Type: multipart/alternative; boundary="----=_Part_301443_784540807.1522154188151" List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , ------=_Part_301443_784540807.1522154188151 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable unscribed me=C2=A0 On =E2=80=8ETuesday=E2=80=8E, =E2=80=8EMarch=E2=80=8E =E2=80=8E27=E2=80= =8E, =E2=80=8E2018=E2=80=8E =E2=80=8E05=E2=80=8E:=E2=80=8E31=E2=80=8E:=E2= =80=8E31=E2=80=8E =E2=80=8EAM=E2=80=8E =E2=80=8EPDT, Michael Ellerman wrote: =20 =20 Add a definition for cpu_show_spectre_v2() to override the generic version. This has several permuations, though in practice some may not occur we cater for any combination. The most verbose is: =C2=A0 Mitigation: Indirect branch serialisation (kernel only), Indirect =C2=A0 branch cache disabled, ori31 speculation barrier enabled We don't treat the ori31 speculation barrier as a mitigation on its own, because it has to be *used* by code in order to be a mitigation and we don't know if userspace is doing that. So if that's all we see we say: =C2=A0 Vulnerable, ori31 speculation barrier enabled Signed-off-by: Michael Ellerman --- arch/powerpc/kernel/security.c | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/arch/powerpc/kernel/security.c b/arch/powerpc/kernel/security.= c index 0eace3cac818..2cee3dcd231b 100644 --- a/arch/powerpc/kernel/security.c +++ b/arch/powerpc/kernel/security.c @@ -58,3 +58,36 @@ ssize_t cpu_show_spectre_v1(struct device *dev, struct d= evice_attribute *attr, c =20 =C2=A0=C2=A0=C2=A0 return sprintf(buf, "Vulnerable\n"); } + +ssize_t cpu_show_spectre_v2(struct device *dev, struct device_attribute *a= ttr, char *buf) +{ +=C2=A0=C2=A0=C2=A0 bool bcs, ccd, ori; +=C2=A0=C2=A0=C2=A0 struct seq_buf s; + +=C2=A0=C2=A0=C2=A0 seq_buf_init(&s, buf, PAGE_SIZE - 1); + +=C2=A0=C2=A0=C2=A0 bcs =3D security_ftr_enabled(SEC_FTR_BCCTRL_SERIALISED)= ; +=C2=A0=C2=A0=C2=A0 ccd =3D security_ftr_enabled(SEC_FTR_COUNT_CACHE_DISABL= ED); +=C2=A0=C2=A0=C2=A0 ori =3D security_ftr_enabled(SEC_FTR_SPEC_BAR_ORI31); + +=C2=A0=C2=A0=C2=A0 if (bcs || ccd) { +=C2=A0=C2=A0=C2=A0 =C2=A0=C2=A0=C2=A0 seq_buf_printf(&s, "Mitigation: "); + +=C2=A0=C2=A0=C2=A0 =C2=A0=C2=A0=C2=A0 if (bcs) +=C2=A0=C2=A0=C2=A0 =C2=A0=C2=A0=C2=A0 =C2=A0=C2=A0=C2=A0 seq_buf_printf(&s= , "Indirect branch serialisation (kernel only)"); + +=C2=A0=C2=A0=C2=A0 =C2=A0=C2=A0=C2=A0 if (bcs && ccd) +=C2=A0=C2=A0=C2=A0 =C2=A0=C2=A0=C2=A0 =C2=A0=C2=A0=C2=A0 seq_buf_printf(&s= , ", "); + +=C2=A0=C2=A0=C2=A0 =C2=A0=C2=A0=C2=A0 if (ccd) +=C2=A0=C2=A0=C2=A0 =C2=A0=C2=A0=C2=A0 =C2=A0=C2=A0=C2=A0 seq_buf_printf(&s= , "Indirect branch cache disabled"); +=C2=A0=C2=A0=C2=A0 } else +=C2=A0=C2=A0=C2=A0 =C2=A0=C2=A0=C2=A0 seq_buf_printf(&s, "Vulnerable"); + +=C2=A0=C2=A0=C2=A0 if (ori) +=C2=A0=C2=A0=C2=A0 =C2=A0=C2=A0=C2=A0 seq_buf_printf(&s, ", ori31 speculat= ion barrier enabled"); + +=C2=A0=C2=A0=C2=A0 seq_buf_printf(&s, "\n"); + +=C2=A0=C2=A0=C2=A0 return s.len; +} --=20 2.14.1 =20 ------=_Part_301443_784540807.1522154188151 Content-Type: text/html; charset=UTF-8 Content-Transfer-Encoding: quoted-printable
unscribed me 

=20
=20
On =E2=80=8ETuesday=E2=80=8E, =E2=80=8EMarch=E2=80= =8E =E2=80=8E27=E2=80=8E, =E2=80=8E2018=E2=80=8E =E2=80=8E05=E2=80=8E:=E2= =80=8E31=E2=80=8E:=E2=80=8E31=E2=80=8E =E2=80=8EAM=E2=80=8E =E2=80=8EPDT, M= ichael Ellerman <mpe@ellerman.id.au> wrote:


Add a definition for cpu_show_spe= ctre_v2() to override the generic
version. This has sever= al permuations, though in practice some may not
occur we = cater for any combination.

The most ve= rbose is:

  Mitigation: Indirect = branch serialisation (kernel only), Indirect
  branc= h cache disabled, ori31 speculation barrier enabled

We don't treat the ori31 speculation barrier as a mitigation = on its
own, because it has to be *used* by code in order = to be a mitigation
and we don't know if userspace is doin= g that. So if that's all we see
we say:

  Vulnerable, ori31 speculation barrier enabled
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
---
arch/powerpc/kernel/security.c | 33 +++++++++++++++++++++++++++++++++<= br clear=3D"none"> 1 file changed, 33 insertions(+)

diff --git a/arch/powerpc/kernel/security.c b/arch/powerpc/ke= rnel/security.c
index 0eace3cac818..2cee3dcd231b 100644--- a/arch/powerpc/kernel/security.c
+++= b/arch/powerpc/kernel/security.c
@@ -58,3 +58,36 @@ ssiz= e_t cpu_show_spectre_v1(struct device *dev, struct device_attribute *attr, = c

    return sprintf(= buf, "Vulnerable\n");
}
+
+ssize_t cpu_show_spectre_v2(struct device *dev, struct device_attrib= ute *attr, char *buf)
+{
+  &= nbsp; bool bcs, ccd, ori;
+    struct seq_= buf s;
+
+    seq_buf_in= it(&s, buf, PAGE_SIZE - 1);
+
+&nbs= p;   bcs =3D security_ftr_enabled(SEC_FTR_BCCTRL_SERIALISED);
+    ccd =3D security_ftr_enabled(SEC_FTR_COU= NT_CACHE_DISABLED);
+    ori =3D security_= ftr_enabled(SEC_FTR_SPEC_BAR_ORI31);
+
= +    if (bcs || ccd) {
+   =     seq_buf_printf(&s, "Mitigation: ");
+
+        if (bcs)
+            seq= _buf_printf(&s, "Indirect branch serialisation (kernel only)");
+
+        if (b= cs && ccd)
+       =     seq_buf_printf(&s, ", ");
+
+        if (ccd)
+            seq_buf_print= f(&s, "Indirect branch cache disabled");
+  = ;  } else
+        seq= _buf_printf(&s, "Vulnerable");
+
+&= nbsp;   if (ori)
+     &nbs= p;  seq_buf_printf(&s, ", ori31 speculation barrier enabled");
+
+    seq_buf_printf(&= s, "\n");
+
+    return = s.len;

+}<= br clear=3D"none">--
2.14.1

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