From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
To: "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com>,
paulus@samba.org, mpe@ellerman.id.au
Cc: linuxppc-dev@lists.ozlabs.org
Subject: Re: [PATCH] powerpc/mm/radix: Update LPCR HR bit as per ISA
Date: Fri, 03 Jun 2016 11:01:51 +1000 [thread overview]
Message-ID: <1464915711.26773.6.camel@kernel.crashing.org> (raw)
In-Reply-To: <1464860457-29253-1-git-send-email-aneesh.kumar@linux.vnet.ibm.com>
On Thu, 2016-06-02 at 15:10 +0530, Aneesh Kumar K.V wrote:
> We need to se HR bit LPCR for radix partitions.
Again (:-) pleaaaaase.... a better changeset description. In fact this
one is actually incorrect, this is not a partition.
Something like "The processor requires the MMU mode (radix vs. hash) of
the hypervisor to be mirrored in the LPCR register, in addition to the
partition table, so as to avoid fetching from the table when deciding,
among other things, how to perform transitions to HV mode on some
interrupts. So let's set it up appropriately".
Cheers,
Ben.
> Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
> ---
> arch/powerpc/include/asm/reg.h | 1 +
> arch/powerpc/mm/pgtable-radix.c | 4 ++--
> 2 files changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/arch/powerpc/include/asm/reg.h
> b/arch/powerpc/include/asm/reg.h
> index c1e82e968506..652147ef5ae3 100644
> --- a/arch/powerpc/include/asm/reg.h
> +++ b/arch/powerpc/include/asm/reg.h
> @@ -348,6 +348,7 @@
> #define LPCR_RMI 0x00000002 /* real mode is cache inhibit
> */
> #define LPCR_HDICE 0x00000001 /* Hyp Decr enable (HV,PR,EE)
> */
> #define LPCR_UPRT 0x00400000 /* Use Process Table (ISA 3)
> */
> +#define LPCR_HR 0x00100000
> #ifndef SPRN_LPID
> #define SPRN_LPID 0x13F /* Logical Partition
> Identifier */
> #endif
> diff --git a/arch/powerpc/mm/pgtable-radix.c
> b/arch/powerpc/mm/pgtable-radix.c
> index c939e6e57a9e..73aa402047ef 100644
> --- a/arch/powerpc/mm/pgtable-radix.c
> +++ b/arch/powerpc/mm/pgtable-radix.c
> @@ -340,7 +340,7 @@ void __init radix__early_init_mmu(void)
> radix_init_page_sizes();
> if (!firmware_has_feature(FW_FEATURE_LPAR)) {
> lpcr = mfspr(SPRN_LPCR);
> - mtspr(SPRN_LPCR, lpcr | LPCR_UPRT);
> + mtspr(SPRN_LPCR, lpcr | LPCR_UPRT | LPCR_HR);
> radix_init_partition_table();
> }
>
> @@ -355,7 +355,7 @@ void radix__early_init_mmu_secondary(void)
> */
> if (!firmware_has_feature(FW_FEATURE_LPAR)) {
> lpcr = mfspr(SPRN_LPCR);
> - mtspr(SPRN_LPCR, lpcr | LPCR_UPRT);
> + mtspr(SPRN_LPCR, lpcr | LPCR_UPRT | LPCR_HR);
>
> mtspr(SPRN_PTCR,
> __pa(partition_tb) | (PATB_SIZE_SHIFT - 12));
next prev parent reply other threads:[~2016-06-03 1:02 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-06-02 9:40 [PATCH] powerpc/mm/radix: Update LPCR HR bit as per ISA Aneesh Kumar K.V
2016-06-03 1:01 ` Benjamin Herrenschmidt [this message]
2016-06-08 4:33 ` Michael Ellerman
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1464915711.26773.6.camel@kernel.crashing.org \
--to=benh@kernel.crashing.org \
--cc=aneesh.kumar@linux.vnet.ibm.com \
--cc=linuxppc-dev@lists.ozlabs.org \
--cc=mpe@ellerman.id.au \
--cc=paulus@samba.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).