From: "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com>
To: benh@kernel.crashing.org, paulus@samba.org, mpe@ellerman.id.au
Cc: linuxppc-dev@lists.ozlabs.org,
"Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com>
Subject: [PATCH V2 09/10] powerpc/mm: Print formation regarding the the MMU mode
Date: Wed, 8 Jun 2016 19:55:57 +0530 [thread overview]
Message-ID: <1465395958-21349-10-git-send-email-aneesh.kumar@linux.vnet.ibm.com> (raw)
In-Reply-To: <1465395958-21349-1-git-send-email-aneesh.kumar@linux.vnet.ibm.com>
This helps in easily identifying the MMU mode with which the kernel
is operating.
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
---
arch/powerpc/mm/hash_utils_64.c | 3 ++-
arch/powerpc/mm/pgtable-radix.c | 3 ++-
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/mm/hash_utils_64.c b/arch/powerpc/mm/hash_utils_64.c
index b2740c67e172..bf9b0b80bbfc 100644
--- a/arch/powerpc/mm/hash_utils_64.c
+++ b/arch/powerpc/mm/hash_utils_64.c
@@ -720,7 +720,7 @@ static void __init hash_init_partition_table(phys_addr_t hash_table,
* For now UPRT is 0 for us.
*/
partition_tb->patb1 = 0;
- DBG("Partition table %p\n", partition_tb);
+ pr_info("Partition table %p\n", partition_tb);
/*
* update partition table control register,
* 64 K size.
@@ -924,6 +924,7 @@ void __init hash__early_init_mmu(void)
*/
htab_initialize();
+ pr_info("Initializing hash mmu with SLB\n");
/* Initialize SLB management */
slb_initialize();
}
diff --git a/arch/powerpc/mm/pgtable-radix.c b/arch/powerpc/mm/pgtable-radix.c
index 73aa402047ef..d6598cd1c3e6 100644
--- a/arch/powerpc/mm/pgtable-radix.c
+++ b/arch/powerpc/mm/pgtable-radix.c
@@ -185,7 +185,8 @@ static void __init radix_init_partition_table(void)
partition_tb = early_alloc_pgtable(1UL << PATB_SIZE_SHIFT);
partition_tb->patb0 = cpu_to_be64(rts_field | __pa(init_mm.pgd) |
RADIX_PGD_INDEX_SIZE | PATB_HR);
- printk("Partition table %p\n", partition_tb);
+ pr_info("Initializing Radix MMU\n");
+ pr_info("Partition table %p\n", partition_tb);
memblock_set_current_limit(MEMBLOCK_ALLOC_ANYWHERE);
/*
--
2.7.4
next prev parent reply other threads:[~2016-06-08 14:26 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-06-08 14:25 [PATCH V2 00/10] Fixes for Radix support Aneesh Kumar K.V
2016-06-08 14:25 ` [PATCH V2 01/10] Fix .long's in mm/tlb-radix.c to more meaningful Aneesh Kumar K.V
2016-06-08 14:25 ` [PATCH V2 02/10] powerpc/mm/radix: Update to tlb functions ric argument Aneesh Kumar K.V
2016-06-15 12:37 ` [V2, " Michael Ellerman
2016-06-08 14:25 ` [PATCH V2 03/10] powerpc/mm/radix: Flush page walk cache when freeing page table Aneesh Kumar K.V
2016-06-15 12:37 ` [V2, " Michael Ellerman
2016-06-08 14:25 ` [PATCH V2 04/10] powerpc/mm/radix: Update LPCR HR bit as per ISA Aneesh Kumar K.V
2016-06-08 14:25 ` [PATCH V2 05/10] powerpc/mm: use _raw variant of page table accessors Aneesh Kumar K.V
2016-06-08 14:25 ` [PATCH V2 06/10] powerpc/mm: Compile out radix related functions if RADIX_MMU is disabled Aneesh Kumar K.V
2016-06-08 14:25 ` [PATCH V2 07/10] powerpc/hash: Use the correct ppp mask when updating hpte Aneesh Kumar K.V
2016-06-15 12:37 ` [V2, " Michael Ellerman
2016-06-08 14:25 ` [PATCH V2 08/10] powerpc/mm: Clear top 16 bits of va only on older cpus Aneesh Kumar K.V
2016-06-09 6:19 ` Aneesh Kumar K.V
2016-06-14 4:57 ` [V2, " Michael Ellerman
2016-06-14 7:13 ` Aneesh Kumar K.V
2016-06-08 14:25 ` Aneesh Kumar K.V [this message]
2016-06-08 14:25 ` [PATCH V2 10/10] powerpc/mm/hash: Update SDR1 size encoding as documented in ISA 3.0 Aneesh Kumar K.V
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