From: "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com>
To: benh@kernel.crashing.org, paulus@samba.org, mpe@ellerman.id.au
Cc: linuxppc-dev@lists.ozlabs.org,
"Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com>
Subject: [PATCH V2 07/10] powerpc/hash: Use the correct ppp mask when updating hpte
Date: Wed, 8 Jun 2016 19:55:55 +0530 [thread overview]
Message-ID: <1465395958-21349-8-git-send-email-aneesh.kumar@linux.vnet.ibm.com> (raw)
In-Reply-To: <1465395958-21349-1-git-send-email-aneesh.kumar@linux.vnet.ibm.com>
With commit: e58e87adc8bf9 ("powerpc/mm: Update _PAGE_KERNEL_RO") we
now use all the three PPP bits. The top bit is now used to have a
PPP value of 0b110 which will be mapped to kernel read only. When
updating the hpte entry use right mask such that we update the
63rd bit (top 'P' bit) too.
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
---
arch/powerpc/include/asm/book3s/64/mmu-hash.h | 1 +
arch/powerpc/mm/hash_native_64.c | 8 ++++----
2 files changed, 5 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/include/asm/book3s/64/mmu-hash.h b/arch/powerpc/include/asm/book3s/64/mmu-hash.h
index 290157e8d5b2..74839f24f412 100644
--- a/arch/powerpc/include/asm/book3s/64/mmu-hash.h
+++ b/arch/powerpc/include/asm/book3s/64/mmu-hash.h
@@ -88,6 +88,7 @@
#define HPTE_R_RPN_SHIFT 12
#define HPTE_R_RPN ASM_CONST(0x0ffffffffffff000)
#define HPTE_R_PP ASM_CONST(0x0000000000000003)
+#define HPTE_R_PPP ASM_CONST(0x8000000000000003)
#define HPTE_R_N ASM_CONST(0x0000000000000004)
#define HPTE_R_G ASM_CONST(0x0000000000000008)
#define HPTE_R_M ASM_CONST(0x0000000000000010)
diff --git a/arch/powerpc/mm/hash_native_64.c b/arch/powerpc/mm/hash_native_64.c
index d873f6507f72..e37916cbc18d 100644
--- a/arch/powerpc/mm/hash_native_64.c
+++ b/arch/powerpc/mm/hash_native_64.c
@@ -316,8 +316,8 @@ static long native_hpte_updatepp(unsigned long slot, unsigned long newpp,
DBG_LOW(" -> hit\n");
/* Update the HPTE */
hptep->r = cpu_to_be64((be64_to_cpu(hptep->r) &
- ~(HPTE_R_PP | HPTE_R_N)) |
- (newpp & (HPTE_R_PP | HPTE_R_N |
+ ~(HPTE_R_PPP | HPTE_R_N)) |
+ (newpp & (HPTE_R_PPP | HPTE_R_N |
HPTE_R_C)));
}
native_unlock_hpte(hptep);
@@ -385,8 +385,8 @@ static void native_hpte_updateboltedpp(unsigned long newpp, unsigned long ea,
/* Update the HPTE */
hptep->r = cpu_to_be64((be64_to_cpu(hptep->r) &
- ~(HPTE_R_PP | HPTE_R_N)) |
- (newpp & (HPTE_R_PP | HPTE_R_N)));
+ ~(HPTE_R_PPP | HPTE_R_N)) |
+ (newpp & (HPTE_R_PPP | HPTE_R_N)));
/*
* Ensure it is out of the tlb too. Bolted entries base and
* actual page size will be same.
--
2.7.4
next prev parent reply other threads:[~2016-06-08 14:26 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-06-08 14:25 [PATCH V2 00/10] Fixes for Radix support Aneesh Kumar K.V
2016-06-08 14:25 ` [PATCH V2 01/10] Fix .long's in mm/tlb-radix.c to more meaningful Aneesh Kumar K.V
2016-06-08 14:25 ` [PATCH V2 02/10] powerpc/mm/radix: Update to tlb functions ric argument Aneesh Kumar K.V
2016-06-15 12:37 ` [V2, " Michael Ellerman
2016-06-08 14:25 ` [PATCH V2 03/10] powerpc/mm/radix: Flush page walk cache when freeing page table Aneesh Kumar K.V
2016-06-15 12:37 ` [V2, " Michael Ellerman
2016-06-08 14:25 ` [PATCH V2 04/10] powerpc/mm/radix: Update LPCR HR bit as per ISA Aneesh Kumar K.V
2016-06-08 14:25 ` [PATCH V2 05/10] powerpc/mm: use _raw variant of page table accessors Aneesh Kumar K.V
2016-06-08 14:25 ` [PATCH V2 06/10] powerpc/mm: Compile out radix related functions if RADIX_MMU is disabled Aneesh Kumar K.V
2016-06-08 14:25 ` Aneesh Kumar K.V [this message]
2016-06-15 12:37 ` [V2, 07/10] powerpc/hash: Use the correct ppp mask when updating hpte Michael Ellerman
2016-06-08 14:25 ` [PATCH V2 08/10] powerpc/mm: Clear top 16 bits of va only on older cpus Aneesh Kumar K.V
2016-06-09 6:19 ` Aneesh Kumar K.V
2016-06-14 4:57 ` [V2, " Michael Ellerman
2016-06-14 7:13 ` Aneesh Kumar K.V
2016-06-08 14:25 ` [PATCH V2 09/10] powerpc/mm: Print formation regarding the the MMU mode Aneesh Kumar K.V
2016-06-08 14:25 ` [PATCH V2 10/10] powerpc/mm/hash: Update SDR1 size encoding as documented in ISA 3.0 Aneesh Kumar K.V
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