Re: [PATCH v5 08/11] powerpc/powernv: Add platform support for stop instruction

[Michael Neuling <mikey@neuling.org>]

On Wed, 2016-06-08 at 22:31 +0530, Shreyas B Prabhu wrote:
> Hi Ben,
>=20
> Sorry for the delayed response.
>=20
> On 06/06/2016 03:58 AM, Benjamin Herrenschmidt wrote:
> >=20
> > On Thu, 2016-06-02 at 07:38 -0500, Shreyas B. Prabhu wrote:
> > >=20
> > > @@ -61,8 +72,13 @@ save_sprs_to_stack:
> > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0* Note all regi=
ster i.e per-core, per-subcore or per-thread
> > > is saved
> > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0* here since an=
y thread in the core might wake up first
> > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0*/
> > > +BEGIN_FTR_SECTION
> > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0mfspr=C2=A0=C2=A0=C2=A0r3,=
SPRN_PTCR
> > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0std=C2=A0=C2=A0=C2=A0=C2=
=A0=C2=A0r3,_PTCR(r1)
> > > +FTR_SECTION_ELSE
> > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0mfspr=C2=A0=C2=A0=C2=
=A0r3,SPRN_SDR1
> > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0std=C2=A0=C2=A0=C2=A0=
=C2=A0=C2=A0r3,_SDR1(r1)
> > > +ALT_FTR_SECTION_END_IFSET(CPU_FTR_ARCH_300)
> > This is the only new SPR we care about in P9 ?
> >=20
> After reviewing ISA again, I've identified LMRR, LMSER and ASDR also
> need to be restored. I've fixed this in v6.

LMRR and LMSER are used the load monitored patch set. =C2=A0There they will=
 get
restored when we context switch back to userspace. =C2=A0It probably doesn'=
t
hurt that much but you don't need to restore them here.=C2=A0

They are not used in the kernel.

It escapes me what ASDR is right now.

Mikey