From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
To: Gavin Shan <gwshan@linux.vnet.ibm.com>
Cc: linuxppc dev list <linuxppc-dev@lists.ozlabs.org>
Subject: Re: [PATCH 3/3] powerpc/pnv/pci: Fix incorrect PE reservation attempt on some 64-bit BARs
Date: Thu, 23 Jun 2016 01:43:23 +1000 [thread overview]
Message-ID: <1466610203.11733.8.camel@kernel.crashing.org> (raw)
In-Reply-To: <20160622103219.GA5978@gwshan>
On Wed, 2016-06-22 at 20:32 +1000, Gavin Shan wrote:
> In pci_read_bridge_mmio_pref(), no prefetchable window (64bits+pref)
> is populated if bit PCI_PREF_RANGE_TYPE_64 (0x1) isn't set on PCI
> config register (PCI_PREF_MEMORY_BASE, 0x24). During the resource
> resizing and assigning stage in PCI core, all resources including
> 64-bits prefetchable resources will be covered by 32-bits bridge
> window.
Yeah ok, that's it, thanks !
Cheers,
Ben.
prev parent reply other threads:[~2016-06-22 15:43 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-06-22 7:26 [PATCH 3/3] powerpc/pnv/pci: Fix incorrect PE reservation attempt on some 64-bit BARs Benjamin Herrenschmidt
2016-06-22 10:32 ` Gavin Shan
2016-06-22 15:43 ` Benjamin Herrenschmidt [this message]
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