From: "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com>
To: benh@kernel.crashing.org, paulus@samba.org, mpe@ellerman.id.au
Cc: linuxppc-dev@lists.ozlabs.org,
Balbir Singh <bsingharora@gmail.com>,
"Aneesh Kumar K . V" <aneesh.kumar@linux.vnet.ibm.com>
Subject: [PATCH for-4.8 01/12] Fix .long's in mm/tlb-radix.c to more meaningful
Date: Wed, 13 Jul 2016 15:05:20 +0530 [thread overview]
Message-ID: <1468402531-4914-2-git-send-email-aneesh.kumar@linux.vnet.ibm.com> (raw)
In-Reply-To: <1468402531-4914-1-git-send-email-aneesh.kumar@linux.vnet.ibm.com>
From: Balbir Singh <bsingharora@gmail.com>
The .longs with the shifts are harder to read, use more
meaningful names for the opcodes. PPC_TLBIE_5 is introduced
for the 5 opcode variation of the instruction due to an existing
op-code for the 2 opcode variant
Signed-off-by: Balbir Singh <bsingharora@gmail.com>
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
---
arch/powerpc/include/asm/ppc-opcode.h | 14 ++++++++++++++
arch/powerpc/mm/tlb-radix.c | 13 +++++--------
2 files changed, 19 insertions(+), 8 deletions(-)
diff --git a/arch/powerpc/include/asm/ppc-opcode.h b/arch/powerpc/include/asm/ppc-opcode.h
index 9de9df14a8d9..1c9b1d4386ba 100644
--- a/arch/powerpc/include/asm/ppc-opcode.h
+++ b/arch/powerpc/include/asm/ppc-opcode.h
@@ -190,6 +190,7 @@
#define PPC_INST_STSWX 0x7c00052a
#define PPC_INST_STXVD2X 0x7c000798
#define PPC_INST_TLBIE 0x7c000264
+#define PPC_INST_TLBIEL 0x7c000224
#define PPC_INST_TLBILX 0x7c000024
#define PPC_INST_WAIT 0x7c00007c
#define PPC_INST_TLBIVAX 0x7c000624
@@ -279,6 +280,9 @@
#define ___PPC_RB(b) (((b) & 0x1f) << 11)
#define ___PPC_RS(s) (((s) & 0x1f) << 21)
#define ___PPC_RT(t) ___PPC_RS(t)
+#define ___PPC_R(r) (((r) & 0x1) << 16)
+#define ___PPC_PRS(prs) (((prs) & 0x1) << 17)
+#define ___PPC_RIC(ric) (((ric) & 0x3) << 18)
#define __PPC_RA(a) ___PPC_RA(__REG_##a)
#define __PPC_RA0(a) ___PPC_RA(__REGA0_##a)
#define __PPC_RB(b) ___PPC_RB(__REG_##b)
@@ -345,6 +349,16 @@
__PPC_WC(w))
#define PPC_TLBIE(lp,a) stringify_in_c(.long PPC_INST_TLBIE | \
___PPC_RB(a) | ___PPC_RS(lp))
+#define PPC_TLBIE_5(rb,rs,ric,prs,r) \
+ stringify_in_c(.long PPC_INST_TLBIE | \
+ ___PPC_RB(rb) | ___PPC_RS(rs) | \
+ ___PPC_RIC(ric) | ___PPC_PRS(prs) | \
+ ___PPC_R(r))
+#define PPC_TLBIEL(rb,rs,ric,prs,r) \
+ stringify_in_c(.long PPC_INST_TLBIEL | \
+ ___PPC_RB(rb) | ___PPC_RS(rs) | \
+ ___PPC_RIC(ric) | ___PPC_PRS(prs) | \
+ ___PPC_R(r))
#define PPC_TLBSRX_DOT(a,b) stringify_in_c(.long PPC_INST_TLBSRX_DOT | \
__PPC_RA0(a) | __PPC_RB(b))
#define PPC_TLBIVAX(a,b) stringify_in_c(.long PPC_INST_TLBIVAX | \
diff --git a/arch/powerpc/mm/tlb-radix.c b/arch/powerpc/mm/tlb-radix.c
index ab2f60e812e2..35690c41f85d 100644
--- a/arch/powerpc/mm/tlb-radix.c
+++ b/arch/powerpc/mm/tlb-radix.c
@@ -12,6 +12,7 @@
#include <linux/mm.h>
#include <linux/hugetlb.h>
#include <linux/memblock.h>
+#include <asm/ppc-opcode.h>
#include <asm/tlb.h>
#include <asm/tlbflush.h>
@@ -34,8 +35,7 @@ static inline void __tlbiel_pid(unsigned long pid, int set,
r = 1; /* raidx format */
asm volatile("ptesync": : :"memory");
- asm volatile(".long 0x7c000224 | (%0 << 11) | (%1 << 16) |"
- "(%2 << 17) | (%3 << 18) | (%4 << 21)"
+ asm volatile(PPC_TLBIEL(%0, %4, %3, %2, %1)
: : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
asm volatile("ptesync": : :"memory");
}
@@ -63,8 +63,7 @@ static inline void _tlbie_pid(unsigned long pid, unsigned long ric)
r = 1; /* raidx format */
asm volatile("ptesync": : :"memory");
- asm volatile(".long 0x7c000264 | (%0 << 11) | (%1 << 16) |"
- "(%2 << 17) | (%3 << 18) | (%4 << 21)"
+ asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
: : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
asm volatile("eieio; tlbsync; ptesync": : :"memory");
}
@@ -81,8 +80,7 @@ static inline void _tlbiel_va(unsigned long va, unsigned long pid,
r = 1; /* raidx format */
asm volatile("ptesync": : :"memory");
- asm volatile(".long 0x7c000224 | (%0 << 11) | (%1 << 16) |"
- "(%2 << 17) | (%3 << 18) | (%4 << 21)"
+ asm volatile(PPC_TLBIEL(%0, %4, %3, %2, %1)
: : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
asm volatile("ptesync": : :"memory");
}
@@ -99,8 +97,7 @@ static inline void _tlbie_va(unsigned long va, unsigned long pid,
r = 1; /* raidx format */
asm volatile("ptesync": : :"memory");
- asm volatile(".long 0x7c000264 | (%0 << 11) | (%1 << 16) |"
- "(%2 << 17) | (%3 << 18) | (%4 << 21)"
+ asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
: : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
asm volatile("eieio; tlbsync; ptesync": : :"memory");
}
--
2.7.4
next prev parent reply other threads:[~2016-07-13 9:35 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-07-13 9:35 [PATCH for-4.8_set1 00/12] Radix fixes for 4.8 Aneesh Kumar K.V
2016-07-13 9:35 ` Aneesh Kumar K.V [this message]
2016-07-17 10:28 ` [for-4.8,01/12] Fix .long's in mm/tlb-radix.c to more meaningful Michael Ellerman
2016-07-13 9:35 ` [PATCH for-4.8 02/12] powerpc/mm/radix: Update LPCR HR bit as per ISA Aneesh Kumar K.V
2016-07-14 3:30 ` Balbir Singh
2016-07-13 9:35 ` [PATCH for-4.8 03/12] powerpc/mm: use _raw variant of page table accessors Aneesh Kumar K.V
2016-07-14 3:42 ` Balbir Singh
2016-07-15 11:42 ` David Laight
2016-07-17 5:22 ` Anton Blanchard
2016-07-13 9:35 ` [PATCH for-4.8 04/12] powerpc/mm: Compile out radix related functions if RADIX_MMU is disabled Aneesh Kumar K.V
2016-07-13 9:35 ` [PATCH for-4.8 05/12] powerpc/mm: Clear top 16 bits of va only on older cpus Aneesh Kumar K.V
2016-07-14 3:50 ` Balbir Singh
2016-07-13 9:35 ` [PATCH for-4.8 06/12] powerpc/mm: Print formation regarding the the MMU mode Aneesh Kumar K.V
2016-07-14 4:03 ` Balbir Singh
2016-07-13 9:35 ` [PATCH for-4.8 07/12] powerpc/mm/hash: Update SDR1 size encoding as documented in ISA 3.0 Aneesh Kumar K.V
2016-07-14 4:29 ` Balbir Singh
2016-07-13 9:35 ` [PATCH for-4.8 08/12] powerpc/mm/radix: Update PID switch sequence Aneesh Kumar K.V
2016-07-13 9:35 ` [PATCH for-4.8 09/12] powerpc/mm/radix: Update machine call back to support new HCALL Aneesh Kumar K.V
2016-07-13 9:35 ` [PATCH for-4.8 10/12] powerpc/mm/radix: Add LPID based tlb flush helpers Aneesh Kumar K.V
2016-07-14 5:12 ` Balbir Singh
2016-07-13 9:35 ` [PATCH for-4.8 11/12] powerpc/mm: Cleanup LPCR defines Aneesh Kumar K.V
2016-07-13 9:35 ` [PATCH for-4.8 12/12] powerpc/mm/radix: Add a kernel command line to disable radix Aneesh Kumar K.V
2016-07-14 5:02 ` Balbir Singh
2016-07-14 8:43 ` Aneesh Kumar K.V
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