* [RFC:PATCH 01/03] powerpc: Extended ptrace interface
2009-12-10 15:57 [RFC:PATCH 00/03] powerpc: Expose BookE debug registers through extended ptrace interface Dave Kleikamp
@ 2009-12-10 15:57 ` Dave Kleikamp
2009-12-11 0:44 ` David Gibson
2009-12-11 2:51 ` Kumar Gala
0 siblings, 2 replies; 9+ messages in thread
From: Dave Kleikamp @ 2009-12-10 15:57 UTC (permalink / raw)
To: linuxppc-dev list
Cc: Sergio Durigan Junior, Thiago Jung Bauermann, Torez Smith,
David Gibson
powerpc: Extended ptrace interface
From: Torez Smith <lnxtorez@linux.vnet.ibm.com>
Add a new extended ptrace interface so that user-space has a single
interface for powerpc, without having to know the specific layout
of the debug registers.
Implement:
PPC_PTRACE_GETHWDEBUGINFO
PPC_PTRACE_SETHWDEBUG
PPC_PTRACE_DELHWDEBUG
Signed-off-by: Dave Kleikamp <shaggy@linux.vnet.ibm.com>
Signed-off-by: Torez Smith <lnxtorez@linux.vnet.ibm.com>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: Thiago Jung Bauermann <bauerman@br.ibm.com>
Cc: Sergio Durigan Junior <sergiodj@br.ibm.com>
Cc: David Gibson <dwg@au1.ibm.com>
Cc: linuxppc-dev list <Linuxppc-dev@ozlabs.org>
---
arch/powerpc/include/asm/ptrace.h | 75 ++++++++++++++++++++++++++++++++
arch/powerpc/kernel/ptrace.c | 88 +++++++++++++++++++++++++++++++++++++
2 files changed, 163 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/include/asm/ptrace.h b/arch/powerpc/include/asm/ptrace.h
index 8c34149..7ae887b 100644
--- a/arch/powerpc/include/asm/ptrace.h
+++ b/arch/powerpc/include/asm/ptrace.h
@@ -24,6 +24,12 @@
* 2 of the License, or (at your option) any later version.
*/
+#ifdef __KERNEL__
+#include <linux/types.h>
+#else
+#include <stdint.h>
+#endif
+
#ifndef __ASSEMBLY__
struct pt_regs {
@@ -292,4 +298,73 @@ extern void user_disable_single_step(struct task_struct *);
#define PTRACE_SINGLEBLOCK 0x100 /* resume execution until next branch */
+#define PPC_PTRACE_GETHWDBGINFO 0x89
+#define PPC_PTRACE_SETHWDEBUG 0x88
+#define PPC_PTRACE_DELHWDEBUG 0x87
+
+#ifndef __ASSEMBLY__
+
+struct ppc_debug_info {
+ uint32_t version; /* Only version 1 exists to date */
+ uint32_t num_instruction_bps;
+ uint32_t num_data_bps;
+ uint32_t num_condition_regs;
+ uint32_t data_bp_alignment;
+ uint32_t sizeof_condition; /* size of the DVC register */
+ uint64_t features;
+};
+
+#endif /* __ASSEMBLY__ */
+
+/*
+ * features will have bits indication whether there is support for:
+ */
+#define PPC_DEBUG_FEATURE_INSN_BP_RANGE 0x1
+#define PPC_DEBUG_FEATURE_INSN_BP_MASK 0x2
+#define PPC_DEBUG_FEATURE_DATA_BP_RANGE 0x4
+#define PPC_DEBUG_FEATURE_DATA_BP_MASK 0x8
+
+#ifndef __ASSEMBLY__
+
+struct ppc_hw_breakpoint {
+ uint32_t version; /* currently, version must be 1 */
+ uint32_t trigger_type; /* only some combinations allowed */
+ uint32_t addr_mode; /* address match mode */
+ uint32_t condition_mode; /* break/watchpoint condition flags */
+ uint64_t addr; /* break/watchpoint address */
+ uint64_t addr2; /* range end or mask */
+ uint64_t condition_value; /* contents of the DVC register */
+};
+
+#endif /* __ASSEMBLY__ */
+
+/*
+ * Trigger Type
+ */
+#define PPC_BREAKPOINT_TRIGGER_EXECUTE 0x1
+#define PPC_BREAKPOINT_TRIGGER_READ 0x2
+#define PPC_BREAKPOINT_TRIGGER_WRITE 0x4
+#define PPC_BREAKPOINT_TRIGGER_RW 0x6
+
+/*
+ * Address Mode
+ */
+#define PPC_BREAKPOINT_MODE_EXACT 0x0
+#define PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE 0x1
+#define PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE 0x2
+#define PPC_BREAKPOINT_MODE_MASK 0x3
+
+/*
+ * Condition Mode
+ */
+#define PPC_BREAKPOINT_CONDITION_NONE 0x0
+#define PPC_BREAKPOINT_CONDITION_AND 0x1
+#define PPC_BREAKPOINT_CONDITION_EXACT 0x1
+#define PPC_BREAKPOINT_CONDITION_OR 0x2
+#define PPC_BREAKPOINT_CONDITION_AND_OR 0x3
+#define PPC_BREAKPOINT_CONDITION_BE_ALL 0x00ff0000
+#define PPC_BREAKPOINT_CONDITION_BE_SHIFT 16
+#define PPC_BREAKPOINT_CONDITION_BE(n) \
+ (1<<((n)+PPC_BREAKPOINT_CONDITION_BE_SHIFT))
+
#endif /* _ASM_POWERPC_PTRACE_H */
diff --git a/arch/powerpc/kernel/ptrace.c b/arch/powerpc/kernel/ptrace.c
index ef14988..6be2ce0 100644
--- a/arch/powerpc/kernel/ptrace.c
+++ b/arch/powerpc/kernel/ptrace.c
@@ -839,6 +839,50 @@ void ptrace_disable(struct task_struct *child)
user_disable_single_step(child);
}
+static long ppc_set_hwdebug(struct task_struct *child,
+ struct ppc_hw_breakpoint *bp_info)
+{
+ /*
+ * We currently support one data breakpoint
+ */
+ if (((bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_RW) == 0) ||
+ ((bp_info->trigger_type & ~PPC_BREAKPOINT_TRIGGER_RW) != 0) ||
+ (bp_info->trigger_type != PPC_BREAKPOINT_TRIGGER_WRITE) ||
+ (bp_info->addr_mode != PPC_BREAKPOINT_MODE_EXACT) ||
+ (bp_info->condition_mode != PPC_BREAKPOINT_CONDITION_NONE))
+ return -EINVAL;
+
+ if (child->thread.dabr)
+ return -ENOSPC;
+
+ if ((unsigned long)bp_info->addr >= TASK_SIZE)
+ return -EIO;
+
+ child->thread.dabr = (unsigned long)bp_info->addr;
+#ifdef CONFIG_BOOKE
+ child->thread.dbcr0 = DBCR0_IDM;
+ if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_READ)
+ child->thread.dbcr0 |= DBSR_DAC1R;
+ if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_WRITE)
+ child->thread.dbcr0 |= DBSR_DAC1W;
+ child->thread.regs->msr |= MSR_DE;
+#endif
+ return 1;
+}
+
+static long ppc_del_hwdebug(struct task_struct *child, long addr, long data)
+{
+ if ((data != 1) || (child->thread.dabr == 0))
+ return -EINVAL;
+
+ child->thread.dabr = 0;
+#ifdef CONFIG_BOOKE
+ child->thread.dbcr0 &= ~(DBSR_DAC1R | DBSR_DAC1W | DBCR0_IDM);
+ child->thread.regs->msr &= ~MSR_DE;
+#endif
+ return 0;
+}
+
/*
* Here are the old "legacy" powerpc specific getregs/setregs ptrace calls,
* we mark them as obsolete now, they will be removed in a future version
@@ -932,6 +976,50 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data)
break;
}
+ case PPC_PTRACE_GETHWDBGINFO: {
+ struct ppc_debug_info dbginfo;
+
+ dbginfo.version = 1;
+ dbginfo.num_instruction_bps = 0;
+ dbginfo.num_data_bps = 1;
+ dbginfo.num_condition_regs = 0;
+#ifdef CONFIG_PPC64
+ dbginfo.data_bp_alignment = 8;
+#else
+ dbginfo.data_bp_alignment = 0;
+#endif
+ dbginfo.sizeof_condition = 0;
+ dbginfo.features = 0;
+
+ if (!access_ok(VERIFY_WRITE, data,
+ sizeof(struct ppc_debug_info)))
+ return -EFAULT;
+ ret = __copy_to_user((struct ppc_debug_info __user *)data,
+ &dbginfo, sizeof(struct ppc_debug_info)) ?
+ -EFAULT : 0;
+ break;
+ }
+
+ case PPC_PTRACE_SETHWDEBUG: {
+ struct ppc_hw_breakpoint bp_info;
+
+ if (!access_ok(VERIFY_READ, data,
+ sizeof(struct ppc_hw_breakpoint)))
+ return -EFAULT;
+ ret = __copy_from_user(&bp_info,
+ (struct ppc_hw_breakpoint __user *)data,
+ sizeof(struct ppc_hw_breakpoint)) ?
+ -EFAULT : 0;
+ if (!ret)
+ ret = ppc_set_hwdebug(child, &bp_info);
+ break;
+ }
+
+ case PPC_PTRACE_DELHWDEBUG: {
+ ret = ppc_del_hwdebug(child, addr, data);
+ break;
+ }
+
case PTRACE_GET_DEBUGREG: {
ret = -EINVAL;
/* We only support one DABR and no IABRS at the moment */
--
Dave Kleikamp
IBM Linux Technology Center
^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [RFC:PATCH 01/03] powerpc: Extended ptrace interface
2009-12-10 15:57 ` [RFC:PATCH 01/03] powerpc: Extended " Dave Kleikamp
@ 2009-12-11 0:44 ` David Gibson
2009-12-11 2:51 ` Kumar Gala
1 sibling, 0 replies; 9+ messages in thread
From: David Gibson @ 2009-12-11 0:44 UTC (permalink / raw)
To: Dave Kleikamp
Cc: linuxppc-dev list, Sergio Durigan Junior, Torez Smith,
Thiago Jung Bauermann
On Thu, Dec 10, 2009 at 01:57:15PM -0200, Dave Kleikamp wrote:
> powerpc: Extended ptrace interface
>
> From: Torez Smith <lnxtorez@linux.vnet.ibm.com>
>
> Add a new extended ptrace interface so that user-space has a single
> interface for powerpc, without having to know the specific layout
> of the debug registers.
> Implement:
> PPC_PTRACE_GETHWDEBUGINFO
> PPC_PTRACE_SETHWDEBUG
> PPC_PTRACE_DELHWDEBUG
>
> Signed-off-by: Dave Kleikamp <shaggy@linux.vnet.ibm.com>
> Signed-off-by: Torez Smith <lnxtorez@linux.vnet.ibm.com>
Apart from the data breakpoint alignment for 32-bit systems, all the
comments below are trivial nits, so:
Acked-by: David Gibson <dwg@au1.ibm.com>
[snip]
> +/*
> + * Trigger Type
> + */
> +#define PPC_BREAKPOINT_TRIGGER_EXECUTE 0x1
> +#define PPC_BREAKPOINT_TRIGGER_READ 0x2
> +#define PPC_BREAKPOINT_TRIGGER_WRITE 0x4
> +#define PPC_BREAKPOINT_TRIGGER_RW 0x6
For a little extra safety, I'd tend towards defining the RW constant
in terms of the READ and WRITE constants.
> +
> +/*
> + * Address Mode
> + */
> +#define PPC_BREAKPOINT_MODE_EXACT 0x0
> +#define PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE 0x1
> +#define PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE 0x2
> +#define PPC_BREAKPOINT_MODE_MASK 0x3
> +
> +/*
> + * Condition Mode
> + */
> +#define PPC_BREAKPOINT_CONDITION_NONE 0x0
> +#define PPC_BREAKPOINT_CONDITION_AND 0x1
> +#define PPC_BREAKPOINT_CONDITION_EXACT 0x1
And likewuse define EXACT in terms of AND.
> +#define PPC_BREAKPOINT_CONDITION_OR 0x2
> +#define PPC_BREAKPOINT_CONDITION_AND_OR 0x3
> +#define PPC_BREAKPOINT_CONDITION_BE_ALL 0x00ff0000
> +#define PPC_BREAKPOINT_CONDITION_BE_SHIFT 16
> +#define PPC_BREAKPOINT_CONDITION_BE(n) \
> + (1<<((n)+PPC_BREAKPOINT_CONDITION_BE_SHIFT))
[snip]
> + case PPC_PTRACE_GETHWDBGINFO: {
> + struct ppc_debug_info dbginfo;
> +
> + dbginfo.version = 1;
> + dbginfo.num_instruction_bps = 0;
> + dbginfo.num_data_bps = 1;
> + dbginfo.num_condition_regs = 0;
> +#ifdef CONFIG_PPC64
> + dbginfo.data_bp_alignment = 8;
> +#else
> + dbginfo.data_bp_alignment = 0;
Uh.. this looks wrong. Surely it should be 4.
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [RFC:PATCH 01/03] powerpc: Extended ptrace interface
2009-12-10 15:57 ` [RFC:PATCH 01/03] powerpc: Extended " Dave Kleikamp
2009-12-11 0:44 ` David Gibson
@ 2009-12-11 2:51 ` Kumar Gala
1 sibling, 0 replies; 9+ messages in thread
From: Kumar Gala @ 2009-12-11 2:51 UTC (permalink / raw)
To: Dave Kleikamp
Cc: linuxppc-dev list, Sergio Durigan Junior, Torez Smith,
Thiago Jung Bauermann, David Gibson
On Dec 10, 2009, at 9:57 AM, Dave Kleikamp wrote:
> powerpc: Extended ptrace interface
>=20
> From: Torez Smith <lnxtorez@linux.vnet.ibm.com>
>=20
> Add a new extended ptrace interface so that user-space has a single
> interface for powerpc, without having to know the specific layout
> of the debug registers.
>=20
> Implement:
> PPC_PTRACE_GETHWDEBUGINFO
> PPC_PTRACE_SETHWDEBUG
> PPC_PTRACE_DELHWDEBUG
>=20
> Signed-off-by: Dave Kleikamp <shaggy@linux.vnet.ibm.com>
> Signed-off-by: Torez Smith <lnxtorez@linux.vnet.ibm.com>
> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> Cc: Thiago Jung Bauermann <bauerman@br.ibm.com>
> Cc: Sergio Durigan Junior <sergiodj@br.ibm.com>
> Cc: David Gibson <dwg@au1.ibm.com>
> Cc: linuxppc-dev list <Linuxppc-dev@ozlabs.org>
> ---
>=20
> arch/powerpc/include/asm/ptrace.h | 75 =
++++++++++++++++++++++++++++++++
> arch/powerpc/kernel/ptrace.c | 88 =
+++++++++++++++++++++++++++++++++++++
> 2 files changed, 163 insertions(+), 0 deletions(-)
>=20
>=20
> diff --git a/arch/powerpc/include/asm/ptrace.h =
b/arch/powerpc/include/asm/ptrace.h
> index 8c34149..7ae887b 100644
> --- a/arch/powerpc/include/asm/ptrace.h
> +++ b/arch/powerpc/include/asm/ptrace.h
> @@ -24,6 +24,12 @@
> * 2 of the License, or (at your option) any later version.
> */
>=20
> +#ifdef __KERNEL__
> +#include <linux/types.h>
> +#else
> +#include <stdint.h>
> +#endif
> +
> #ifndef __ASSEMBLY__
>=20
> struct pt_regs {
> @@ -292,4 +298,73 @@ extern void user_disable_single_step(struct =
task_struct *);
>=20
> #define PTRACE_SINGLEBLOCK 0x100 /* resume execution until next =
branch */
>=20
> +#define PPC_PTRACE_GETHWDBGINFO 0x89
> +#define PPC_PTRACE_SETHWDEBUG 0x88
> +#define PPC_PTRACE_DELHWDEBUG 0x87
> +
> +#ifndef __ASSEMBLY__
> +
> +struct ppc_debug_info {
> + uint32_t version; /* Only version 1 exists to date =
*/
> + uint32_t num_instruction_bps;
> + uint32_t num_data_bps;
> + uint32_t num_condition_regs;
> + uint32_t data_bp_alignment;
> + uint32_t sizeof_condition; /* size of the DVC register */
> + uint64_t features;
> +};
> +
> +#endif /* __ASSEMBLY__ */
> +
> +/*
> + * features will have bits indication whether there is support for:
> + */
> +#define PPC_DEBUG_FEATURE_INSN_BP_RANGE 0x1
> +#define PPC_DEBUG_FEATURE_INSN_BP_MASK 0x2
> +#define PPC_DEBUG_FEATURE_DATA_BP_RANGE 0x4
> +#define PPC_DEBUG_FEATURE_DATA_BP_MASK 0x8
Pad these out.
#define PPC_DEBUG_FEATURE_INSN_BP_RANGE 0x0000000000000001
#define PPC_DEBUG_FEATURE_INSN_BP_MASK 0x0000000000000002
etc..
> +
> +#ifndef __ASSEMBLY__
> +
> +struct ppc_hw_breakpoint {
> + uint32_t version; /* currently, version must be 1 =
*/
> + uint32_t trigger_type; /* only some combinations =
allowed */
> + uint32_t addr_mode; /* address match mode */
> + uint32_t condition_mode; /* break/watchpoint condition =
flags */
> + uint64_t addr; /* break/watchpoint address */
> + uint64_t addr2; /* range end or mask */
> + uint64_t condition_value; /* contents of the DVC register =
*/
> +};
> +
> +#endif /* __ASSEMBLY__ */
> +
> +/*
> + * Trigger Type
> + */
> +#define PPC_BREAKPOINT_TRIGGER_EXECUTE 0x1
> +#define PPC_BREAKPOINT_TRIGGER_READ 0x2
> +#define PPC_BREAKPOINT_TRIGGER_WRITE 0x4
> +#define PPC_BREAKPOINT_TRIGGER_RW 0x6
(ditto on the padding)
> +
> +/*
> + * Address Mode
> + */
> +#define PPC_BREAKPOINT_MODE_EXACT 0x0
> +#define PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE 0x1
> +#define PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE 0x2
> +#define PPC_BREAKPOINT_MODE_MASK 0x3
> +
(ditto on the padding)
> +/*
> + * Condition Mode
> + */
> +#define PPC_BREAKPOINT_CONDITION_NONE 0x0
> +#define PPC_BREAKPOINT_CONDITION_AND 0x1
> +#define PPC_BREAKPOINT_CONDITION_EXACT 0x1
> +#define PPC_BREAKPOINT_CONDITION_OR 0x2
> +#define PPC_BREAKPOINT_CONDITION_AND_OR 0x3
(ditto on the padding)
> +#define PPC_BREAKPOINT_CONDITION_BE_ALL 0x00ff0000
> +#define PPC_BREAKPOINT_CONDITION_BE_SHIFT 16
> +#define PPC_BREAKPOINT_CONDITION_BE(n) \
> + (1<<((n)+PPC_BREAKPOINT_CONDITION_BE_SHIFT))
> +
> #endif /* _ASM_POWERPC_PTRACE_H */
> diff --git a/arch/powerpc/kernel/ptrace.c =
b/arch/powerpc/kernel/ptrace.c
> index ef14988..6be2ce0 100644
> --- a/arch/powerpc/kernel/ptrace.c
> +++ b/arch/powerpc/kernel/ptrace.c
> @@ -839,6 +839,50 @@ void ptrace_disable(struct task_struct *child)
> user_disable_single_step(child);
> }
>=20
> +static long ppc_set_hwdebug(struct task_struct *child,
> + struct ppc_hw_breakpoint *bp_info)
> +{
> + /*
> + * We currently support one data breakpoint
> + */
> + if (((bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_RW) =3D=3D =
0) ||
> + ((bp_info->trigger_type & ~PPC_BREAKPOINT_TRIGGER_RW) !=3D =
0) ||
> + (bp_info->trigger_type !=3D PPC_BREAKPOINT_TRIGGER_WRITE) ||
> + (bp_info->addr_mode !=3D PPC_BREAKPOINT_MODE_EXACT) ||
> + (bp_info->condition_mode !=3D =
PPC_BREAKPOINT_CONDITION_NONE))
> + return -EINVAL;
> +
> + if (child->thread.dabr)
> + return -ENOSPC;
> +
> + if ((unsigned long)bp_info->addr >=3D TASK_SIZE)
> + return -EIO;
> +
> + child->thread.dabr =3D (unsigned long)bp_info->addr;
> +#ifdef CONFIG_BOOKE
> + child->thread.dbcr0 =3D DBCR0_IDM;
> + if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_READ)
> + child->thread.dbcr0 |=3D DBSR_DAC1R;
> + if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_WRITE)
> + child->thread.dbcr0 |=3D DBSR_DAC1W;
> + child->thread.regs->msr |=3D MSR_DE;
> +#endif
> + return 1;
> +}
> +
> +static long ppc_del_hwdebug(struct task_struct *child, long addr, =
long data)
> +{
> + if ((data !=3D 1) || (child->thread.dabr =3D=3D 0))
> + return -EINVAL;
> +
> + child->thread.dabr =3D 0;
> +#ifdef CONFIG_BOOKE
> + child->thread.dbcr0 &=3D ~(DBSR_DAC1R | DBSR_DAC1W | DBCR0_IDM);
> + child->thread.regs->msr &=3D ~MSR_DE;
> +#endif
> + return 0;
> +}
> +
> /*
> * Here are the old "legacy" powerpc specific getregs/setregs ptrace =
calls,
> * we mark them as obsolete now, they will be removed in a future =
version
> @@ -932,6 +976,50 @@ long arch_ptrace(struct task_struct *child, long =
request, long addr, long data)
> break;
> }
>=20
> + case PPC_PTRACE_GETHWDBGINFO: {
> + struct ppc_debug_info dbginfo;
> +
> + dbginfo.version =3D 1;
> + dbginfo.num_instruction_bps =3D 0;
> + dbginfo.num_data_bps =3D 1;
> + dbginfo.num_condition_regs =3D 0;
> +#ifdef CONFIG_PPC64
> + dbginfo.data_bp_alignment =3D 8;
> +#else
> + dbginfo.data_bp_alignment =3D 0;
> +#endif
> + dbginfo.sizeof_condition =3D 0;
> + dbginfo.features =3D 0;
> +
> + if (!access_ok(VERIFY_WRITE, data,
> + sizeof(struct ppc_debug_info)))
> + return -EFAULT;
> + ret =3D __copy_to_user((struct ppc_debug_info __user =
*)data,
> + &dbginfo, sizeof(struct =
ppc_debug_info)) ?
> + -EFAULT : 0;
> + break;
> + }
> +
> + case PPC_PTRACE_SETHWDEBUG: {
> + struct ppc_hw_breakpoint bp_info;
> +
> + if (!access_ok(VERIFY_READ, data,
> + sizeof(struct ppc_hw_breakpoint)))
> + return -EFAULT;
> + ret =3D __copy_from_user(&bp_info,
> + (struct ppc_hw_breakpoint __user =
*)data,
> + sizeof(struct ppc_hw_breakpoint)) =
?
> + -EFAULT : 0;
> + if (!ret)
> + ret =3D ppc_set_hwdebug(child, &bp_info);
> + break;
> + }
> +
> + case PPC_PTRACE_DELHWDEBUG: {
> + ret =3D ppc_del_hwdebug(child, addr, data);
> + break;
> + }
> +
> case PTRACE_GET_DEBUGREG: {
> ret =3D -EINVAL;
> /* We only support one DABR and no IABRS at the moment =
*/
>=20
> --=20
> Dave Kleikamp
> IBM Linux Technology Center
> _______________________________________________
> Linuxppc-dev mailing list
> Linuxppc-dev@lists.ozlabs.org
> https://lists.ozlabs.org/listinfo/linuxppc-dev
^ permalink raw reply [flat|nested] 9+ messages in thread
* [RFC:PATCH 00/03] powerpc: Expose BookE debug registers through extended ptrace interface
@ 2010-01-18 21:57 Dave Kleikamp
2010-01-18 21:57 ` [RFC:PATCH 01/03] powerpc: Extended " Dave Kleikamp
` (2 more replies)
0 siblings, 3 replies; 9+ messages in thread
From: Dave Kleikamp @ 2010-01-18 21:57 UTC (permalink / raw)
To: linuxppc-dev list
Cc: Sergio Durigan Junior, David Gibson, Torez Smith,
Thiago Jung Bauermann
These patches implement an extention to the ptrace interface proposed by
Thiago Bauermann and the the PowerPC gdb team.
This is a resubmission of the patches I first sent on December 9th.
Sorry for the delay. I have addressed most of the comments, and I'll
follow up on the others.
These patches are based on 2.6.33-rc3. (Nothing really changed in powerpc
between rc3 & rc4.) These patches still need some testing, but I want
to get the ball rolling again.
The following has been added as Documentation/powerpc/ptrace.txt:
GDB intends to support the following hardware debug features of BookE
processors:
4 hardware breakpoints (IAC)
2 hardware watchpoints (read, write and read-write) (DAC)
2 value conditions for the hardware watchpoints (DVC)
For that, we need to extend ptrace so that GDB can query and set these
resources. Since we're extending, we're trying to create an interface
that's extendable and that covers both BookE and server processors, so
that GDB doesn't need to special-case each of them. We added the
following 3 new ptrace requests.
1. PTRACE_PPC_GETHWDEBUGINFO
Query for GDB to discover the hardware debug features. The main info to
be returned here is the minimum alignment for the hardware watchpoints.
BookE processors don't have restrictions here, but server processors have
an 8-byte alignment restriction for hardware watchpoints. We'd like to avoid
adding special cases to GDB based on what it sees in AUXV.
Since we're at it, we added other useful info that the kernel can return to
GDB: this query will return the number of hardware breakpoints, hardware
watchpoints and whether it supports a range of addresses and a condition.
The query will fill the following structure provided by the requesting process:
struct ppc_debug_info {
unit32_t version;
unit32_t num_instruction_bps;
unit32_t num_data_bps;
unit32_t num_condition_regs;
unit32_t data_bp_alignment;
unit32_t sizeof_condition; /* size of the DVC register */
uint64_t features; /* bitmask of the individual flags */
};
features will have bits indicating whether there is support for:
#define PPC_DEBUG_FEATURE_INSN_BP_RANGE 0x1
#define PPC_DEBUG_FEATURE_INSN_BP_MASK 0x2
#define PPC_DEBUG_FEATURE_DATA_BP_RANGE 0x4
#define PPC_DEBUG_FEATURE_DATA_BP_MASK 0x8
2. PTRACE_SETHWDEBUG
Sets a hardware breakpoint or watchpoint, according to the provided structure:
struct ppc_hw_breakpoint {
uint32_t version;
#define PPC_BREAKPOINT_TRIGGER_EXECUTE 0x1
#define PPC_BREAKPOINT_TRIGGER_READ 0x2
#define PPC_BREAKPOINT_TRIGGER_WRITE 0x4
uint32_t trigger_type; /* only some combinations allowed */
#define PPC_BREAKPOINT_MODE_EXACT 0x0
#define PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE 0x1
#define PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE 0x2
#define PPC_BREAKPOINT_MODE_MASK 0x3
uint32_t addr_mode; /* address match mode */
#define PPC_BREAKPOINT_CONDITION_MODE 0x3
#define PPC_BREAKPOINT_CONDITION_NONE 0x0
#define PPC_BREAKPOINT_CONDITION_AND 0x1
#define PPC_BREAKPOINT_CONDITION_EXACT 0x1 /* different name for the same thing as above */
#define PPC_BREAKPOINT_CONDITION_OR 0x2
#define PPC_BREAKPOINT_CONDITION_AND_OR 0x3
#define PPC_BREAKPOINT_CONDITION_BE_ALL 0x00ff0000 /* byte enable bits */
#define PPC_BREAKPOINT_CONDITION_BE(n) (1<<((n)+16))
uint32_t condition_mode; /* break/watchpoint condition flags */
uint64_t addr;
uint64_t addr2;
uint64_t condition_value;
};
A request specifies one event, not necessarily just one register to be set.
For instance, if the request is for a watchpoint with a condition, both the
DAC and DVC registers will be set in the same request.
With this GDB can ask for all kinds of hardware breakpoints and watchpoints
that the BookE supports. COMEFROM breakpoints available in server processors
are not contemplated, but that is out of the scope of this work.
ptrace will return an integer (handle) uniquely identifying the breakpoint or
watchpoint just created. This integer will be used in the PTRACE_DELHWDEBUG
request to ask for its removal. Return -ENOSPC if the requested breakpoint
can't be allocated on the registers.
Some examples of using the structure to:
- set a breakpoint in the first breakpoint register
p.version = PPC_DEBUG_CURRENT_VERSION;
p.trigger_type = PPC_BREAKPOINT_TRIGGER_EXECUTE;
p.addr_mode = PPC_BREAKPOINT_MODE_EXACT;
p.condition_mode = PPC_BREAKPOINT_CONDITION_NONE;
p.addr = (uint64_t) address;
p.addr2 = 0;
p.condition_value = 0;
- set a watchpoint which triggers on reads in the second watchpoint register
p.version = PPC_DEBUG_CURRENT_VERSION;
p.trigger_type = PPC_BREAKPOINT_TRIGGER_READ;
p.addr_mode = PPC_BREAKPOINT_MODE_EXACT;
p.condition_mode = PPC_BREAKPOINT_CONDITION_NONE;
p.addr = (uint64_t) address;
p.addr2 = 0;
p.condition_value = 0;
- set a watchpoint which triggers only with a specific value
p.version = PPC_DEBUG_CURRENT_VERSION;
p.trigger_type = PPC_BREAKPOINT_TRIGGER_READ;
p.addr_mode = PPC_BREAKPOINT_MODE_EXACT;
p.condition_mode = PPC_BREAKPOINT_CONDITION_AND | PPC_BREAKPOINT_CONDITION_BE_ALL;
p.addr = (uint64_t) address;
p.addr2 = 0;
p.condition_value = (uint64_t) condition;
- set a ranged hardware breakpoint
p.version = PPC_DEBUG_CURRENT_VERSION;
p.trigger_type = PPC_BREAKPOINT_TRIGGER_EXECUTE;
p.addr_mode = PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE;
p.condition_mode = PPC_BREAKPOINT_CONDITION_NONE;
p.addr = (uint64_t) begin_range;
p.addr2 = (uint64_t) end_range;
p.condition_value = 0;
3. PTRACE_DELHWDEBUG
Takes an integer which identifies an existing breakpoint or watchpoint
(i.e., the value returned from PTRACE_SETHWDEBUG), and deletes the
corresponding breakpoint or watchpoint..
--
Dave Kleikamp
IBM Linux Technology Center
^ permalink raw reply [flat|nested] 9+ messages in thread
* [RFC:PATCH 01/03] powerpc: Extended ptrace interface
2010-01-18 21:57 [RFC:PATCH 00/03] powerpc: Expose BookE debug registers through extended ptrace interface Dave Kleikamp
@ 2010-01-18 21:57 ` Dave Kleikamp
2010-01-21 2:47 ` Michael Neuling
2010-01-18 21:57 ` [RFC:PATCH 03/03] powerpc: Add support for BookE Debug Reg. traps, exceptions and ptrace Dave Kleikamp
2010-01-18 21:59 ` [RFC:PATCH 02/03] powerpc: Add definitions for Debug Registers on BookE Platforms Dave Kleikamp
2 siblings, 1 reply; 9+ messages in thread
From: Dave Kleikamp @ 2010-01-18 21:57 UTC (permalink / raw)
To: linuxppc-dev list
Cc: Sergio Durigan Junior, David Gibson, Torez Smith,
Thiago Jung Bauermann
powerpc: Extended ptrace interface
From: Torez Smith <lnxtorez@linux.vnet.ibm.com>
Add a new extended ptrace interface so that user-space has a single
interface for powerpc, without having to know the specific layout
of the debug registers.
Implement:
PPC_PTRACE_GETHWDEBUGINFO
PPC_PTRACE_SETHWDEBUG
PPC_PTRACE_DELHWDEBUG
Signed-off-by: Torez Smith <lnxtorez@linux.vnet.ibm.com>
Signed-off-by: Dave Kleikamp <shaggy@linux.vnet.ibm.com>
Acked-by: David Gibson <dwg@au1.ibm.com>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: Josh Boyer <jwboyer@linux.vnet.ibm.com>
Cc: Kumar Gala <galak@kernel.crashing.org>
Cc: Sergio Durigan Junior <sergiodj@br.ibm.com>
Cc: Thiago Jung Bauermann <bauerman@br.ibm.com>
Cc: linuxppc-dev list <Linuxppc-dev@ozlabs.org>
---
Documentation/powerpc/ptrace.txt | 134 +++++++++++++++++++++++++++++++++++++
arch/powerpc/include/asm/ptrace.h | 77 +++++++++++++++++++++
arch/powerpc/kernel/ptrace.c | 90 +++++++++++++++++++++++++
3 files changed, 301 insertions(+), 0 deletions(-)
create mode 100644 Documentation/powerpc/ptrace.txt
diff --git a/Documentation/powerpc/ptrace.txt b/Documentation/powerpc/ptrace.txt
new file mode 100644
index 0000000..f4a5499
--- /dev/null
+++ b/Documentation/powerpc/ptrace.txt
@@ -0,0 +1,134 @@
+GDB intends to support the following hardware debug features of BookE
+processors:
+
+4 hardware breakpoints (IAC)
+2 hardware watchpoints (read, write and read-write) (DAC)
+2 value conditions for the hardware watchpoints (DVC)
+
+For that, we need to extend ptrace so that GDB can query and set these
+resources. Since we're extending, we're trying to create an interface
+that's extendable and that covers both BookE and server processors, so
+that GDB doesn't need to special-case each of them. We added the
+following 3 new ptrace requests.
+
+1. PTRACE_PPC_GETHWDEBUGINFO
+
+Query for GDB to discover the hardware debug features. The main info to
+be returned here is the minimum alignment for the hardware watchpoints.
+BookE processors don't have restrictions here, but server processors have
+an 8-byte alignment restriction for hardware watchpoints. We'd like to avoid
+adding special cases to GDB based on what it sees in AUXV.
+
+Since we're at it, we added other useful info that the kernel can return to
+GDB: this query will return the number of hardware breakpoints, hardware
+watchpoints and whether it supports a range of addresses and a condition.
+The query will fill the following structure provided by the requesting process:
+
+struct ppc_debug_info {
+ unit32_t version;
+ unit32_t num_instruction_bps;
+ unit32_t num_data_bps;
+ unit32_t num_condition_regs;
+ unit32_t data_bp_alignment;
+ unit32_t sizeof_condition; /* size of the DVC register */
+ uint64_t features; /* bitmask of the individual flags */
+};
+
+features will have bits indicating whether there is support for:
+
+#define PPC_DEBUG_FEATURE_INSN_BP_RANGE 0x1
+#define PPC_DEBUG_FEATURE_INSN_BP_MASK 0x2
+#define PPC_DEBUG_FEATURE_DATA_BP_RANGE 0x4
+#define PPC_DEBUG_FEATURE_DATA_BP_MASK 0x8
+
+2. PTRACE_SETHWDEBUG
+
+Sets a hardware breakpoint or watchpoint, according to the provided structure:
+
+struct ppc_hw_breakpoint {
+ uint32_t version;
+#define PPC_BREAKPOINT_TRIGGER_EXECUTE 0x1
+#define PPC_BREAKPOINT_TRIGGER_READ 0x2
+#define PPC_BREAKPOINT_TRIGGER_WRITE 0x4
+ uint32_t trigger_type; /* only some combinations allowed */
+#define PPC_BREAKPOINT_MODE_EXACT 0x0
+#define PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE 0x1
+#define PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE 0x2
+#define PPC_BREAKPOINT_MODE_MASK 0x3
+ uint32_t addr_mode; /* address match mode */
+
+#define PPC_BREAKPOINT_CONDITION_MODE 0x3
+#define PPC_BREAKPOINT_CONDITION_NONE 0x0
+#define PPC_BREAKPOINT_CONDITION_AND 0x1
+#define PPC_BREAKPOINT_CONDITION_EXACT 0x1 /* different name for the same thing as above */
+#define PPC_BREAKPOINT_CONDITION_OR 0x2
+#define PPC_BREAKPOINT_CONDITION_AND_OR 0x3
+#define PPC_BREAKPOINT_CONDITION_BE_ALL 0x00ff0000 /* byte enable bits */
+#define PPC_BREAKPOINT_CONDITION_BE(n) (1<<((n)+16))
+ uint32_t condition_mode; /* break/watchpoint condition flags */
+
+ uint64_t addr;
+ uint64_t addr2;
+ uint64_t condition_value;
+};
+
+A request specifies one event, not necessarily just one register to be set.
+For instance, if the request is for a watchpoint with a condition, both the
+DAC and DVC registers will be set in the same request.
+
+With this GDB can ask for all kinds of hardware breakpoints and watchpoints
+that the BookE supports. COMEFROM breakpoints available in server processors
+are not contemplated, but that is out of the scope of this work.
+
+ptrace will return an integer (handle) uniquely identifying the breakpoint or
+watchpoint just created. This integer will be used in the PTRACE_DELHWDEBUG
+request to ask for its removal. Return -ENOSPC if the requested breakpoint
+can't be allocated on the registers.
+
+Some examples of using the structure to:
+
+- set a breakpoint in the first breakpoint register
+
+ p.version = PPC_DEBUG_CURRENT_VERSION;
+ p.trigger_type = PPC_BREAKPOINT_TRIGGER_EXECUTE;
+ p.addr_mode = PPC_BREAKPOINT_MODE_EXACT;
+ p.condition_mode = PPC_BREAKPOINT_CONDITION_NONE;
+ p.addr = (uint64_t) address;
+ p.addr2 = 0;
+ p.condition_value = 0;
+
+- set a watchpoint which triggers on reads in the second watchpoint register
+
+ p.version = PPC_DEBUG_CURRENT_VERSION;
+ p.trigger_type = PPC_BREAKPOINT_TRIGGER_READ;
+ p.addr_mode = PPC_BREAKPOINT_MODE_EXACT;
+ p.condition_mode = PPC_BREAKPOINT_CONDITION_NONE;
+ p.addr = (uint64_t) address;
+ p.addr2 = 0;
+ p.condition_value = 0;
+
+- set a watchpoint which triggers only with a specific value
+
+ p.version = PPC_DEBUG_CURRENT_VERSION;
+ p.trigger_type = PPC_BREAKPOINT_TRIGGER_READ;
+ p.addr_mode = PPC_BREAKPOINT_MODE_EXACT;
+ p.condition_mode = PPC_BREAKPOINT_CONDITION_AND | PPC_BREAKPOINT_CONDITION_BE_ALL;
+ p.addr = (uint64_t) address;
+ p.addr2 = 0;
+ p.condition_value = (uint64_t) condition;
+
+- set a ranged hardware breakpoint
+
+ p.version = PPC_DEBUG_CURRENT_VERSION;
+ p.trigger_type = PPC_BREAKPOINT_TRIGGER_EXECUTE;
+ p.addr_mode = PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE;
+ p.condition_mode = PPC_BREAKPOINT_CONDITION_NONE;
+ p.addr = (uint64_t) begin_range;
+ p.addr2 = (uint64_t) end_range;
+ p.condition_value = 0;
+
+3. PTRACE_DELHWDEBUG
+
+Takes an integer which identifies an existing breakpoint or watchpoint
+(i.e., the value returned from PTRACE_SETHWDEBUG), and deletes the
+corresponding breakpoint or watchpoint..
diff --git a/arch/powerpc/include/asm/ptrace.h b/arch/powerpc/include/asm/ptrace.h
index cbd759e..b451081 100644
--- a/arch/powerpc/include/asm/ptrace.h
+++ b/arch/powerpc/include/asm/ptrace.h
@@ -24,6 +24,12 @@
* 2 of the License, or (at your option) any later version.
*/
+#ifdef __KERNEL__
+#include <linux/types.h>
+#else
+#include <stdint.h>
+#endif
+
#ifndef __ASSEMBLY__
struct pt_regs {
@@ -294,4 +300,75 @@ extern void user_disable_single_step(struct task_struct *);
#define PTRACE_SINGLEBLOCK 0x100 /* resume execution until next branch */
+#define PPC_PTRACE_GETHWDBGINFO 0x89
+#define PPC_PTRACE_SETHWDEBUG 0x88
+#define PPC_PTRACE_DELHWDEBUG 0x87
+
+#ifndef __ASSEMBLY__
+
+struct ppc_debug_info {
+ uint32_t version; /* Only version 1 exists to date */
+ uint32_t num_instruction_bps;
+ uint32_t num_data_bps;
+ uint32_t num_condition_regs;
+ uint32_t data_bp_alignment;
+ uint32_t sizeof_condition; /* size of the DVC register */
+ uint64_t features;
+};
+
+#endif /* __ASSEMBLY__ */
+
+/*
+ * features will have bits indication whether there is support for:
+ */
+#define PPC_DEBUG_FEATURE_INSN_BP_RANGE 0x0000000000000001
+#define PPC_DEBUG_FEATURE_INSN_BP_MASK 0x0000000000000002
+#define PPC_DEBUG_FEATURE_DATA_BP_RANGE 0x0000000000000004
+#define PPC_DEBUG_FEATURE_DATA_BP_MASK 0x0000000000000008
+
+#ifndef __ASSEMBLY__
+
+struct ppc_hw_breakpoint {
+ uint32_t version; /* currently, version must be 1 */
+ uint32_t trigger_type; /* only some combinations allowed */
+ uint32_t addr_mode; /* address match mode */
+ uint32_t condition_mode; /* break/watchpoint condition flags */
+ uint64_t addr; /* break/watchpoint address */
+ uint64_t addr2; /* range end or mask */
+ uint64_t condition_value; /* contents of the DVC register */
+};
+
+#endif /* __ASSEMBLY__ */
+
+/*
+ * Trigger Type
+ */
+#define PPC_BREAKPOINT_TRIGGER_EXECUTE 0x00000001
+#define PPC_BREAKPOINT_TRIGGER_READ 0x00000002
+#define PPC_BREAKPOINT_TRIGGER_WRITE 0x00000004
+#define PPC_BREAKPOINT_TRIGGER_RW \
+ (PPC_BREAKPOINT_TRIGGER_READ | PPC_BREAKPOINT_TRIGGER_WRITE)
+
+/*
+ * Address Mode
+ */
+#define PPC_BREAKPOINT_MODE_EXACT 0x00000000
+#define PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE 0x00000001
+#define PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE 0x00000002
+#define PPC_BREAKPOINT_MODE_MASK 0x00000003
+
+/*
+ * Condition Mode
+ */
+#define PPC_BREAKPOINT_CONDITION_MODE 0x00000003
+#define PPC_BREAKPOINT_CONDITION_NONE 0x00000000
+#define PPC_BREAKPOINT_CONDITION_AND 0x00000001
+#define PPC_BREAKPOINT_CONDITION_EXACT PPC_BREAKPOINT_CONDITION_AND
+#define PPC_BREAKPOINT_CONDITION_OR 0x00000002
+#define PPC_BREAKPOINT_CONDITION_AND_OR 0x00000003
+#define PPC_BREAKPOINT_CONDITION_BE_ALL 0x00ff0000
+#define PPC_BREAKPOINT_CONDITION_BE_SHIFT 16
+#define PPC_BREAKPOINT_CONDITION_BE(n) \
+ (1<<((n)+PPC_BREAKPOINT_CONDITION_BE_SHIFT))
+
#endif /* _ASM_POWERPC_PTRACE_H */
diff --git a/arch/powerpc/kernel/ptrace.c b/arch/powerpc/kernel/ptrace.c
index ef14988..33ab496 100644
--- a/arch/powerpc/kernel/ptrace.c
+++ b/arch/powerpc/kernel/ptrace.c
@@ -839,6 +839,52 @@ void ptrace_disable(struct task_struct *child)
user_disable_single_step(child);
}
+static long ppc_set_hwdebug(struct task_struct *child,
+ struct ppc_hw_breakpoint *bp_info)
+{
+ /*
+ * We currently support one data breakpoint
+ */
+ if (((bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_RW) == 0) ||
+ ((bp_info->trigger_type & ~PPC_BREAKPOINT_TRIGGER_RW) != 0) ||
+ (bp_info->trigger_type != PPC_BREAKPOINT_TRIGGER_WRITE) ||
+ (bp_info->addr_mode != PPC_BREAKPOINT_MODE_EXACT) ||
+ (bp_info->condition_mode != PPC_BREAKPOINT_CONDITION_NONE))
+ return -EINVAL;
+
+ if (child->thread.dabr)
+ return -ENOSPC;
+
+ if ((unsigned long)bp_info->addr >= TASK_SIZE)
+ return -EIO;
+
+ child->thread.dabr = (unsigned long)bp_info->addr;
+#ifdef CONFIG_BOOKE
+ child->thread.dbcr0 = DBCR0_IDM;
+ if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_READ)
+ child->thread.dbcr0 |= DBSR_DAC1R;
+ if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_WRITE)
+ child->thread.dbcr0 |= DBSR_DAC1W;
+ child->thread.regs->msr |= MSR_DE;
+#endif
+ return 1;
+}
+
+static long ppc_del_hwdebug(struct task_struct *child, long addr, long data)
+{
+ if (data != 1)
+ return -EINVAL;
+ if (child->thread.dabr == 0)
+ return -ENOENT;
+
+ child->thread.dabr = 0;
+#ifdef CONFIG_BOOKE
+ child->thread.dbcr0 &= ~(DBSR_DAC1R | DBSR_DAC1W | DBCR0_IDM);
+ child->thread.regs->msr &= ~MSR_DE;
+#endif
+ return 0;
+}
+
/*
* Here are the old "legacy" powerpc specific getregs/setregs ptrace calls,
* we mark them as obsolete now, they will be removed in a future version
@@ -932,6 +978,50 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data)
break;
}
+ case PPC_PTRACE_GETHWDBGINFO: {
+ struct ppc_debug_info dbginfo;
+
+ dbginfo.version = 1;
+ dbginfo.num_instruction_bps = 0;
+ dbginfo.num_data_bps = 1;
+ dbginfo.num_condition_regs = 0;
+#ifdef CONFIG_PPC64
+ dbginfo.data_bp_alignment = 8;
+#else
+ dbginfo.data_bp_alignment = 4;
+#endif
+ dbginfo.sizeof_condition = 0;
+ dbginfo.features = 0;
+
+ if (!access_ok(VERIFY_WRITE, data,
+ sizeof(struct ppc_debug_info)))
+ return -EFAULT;
+ ret = __copy_to_user((struct ppc_debug_info __user *)data,
+ &dbginfo, sizeof(struct ppc_debug_info)) ?
+ -EFAULT : 0;
+ break;
+ }
+
+ case PPC_PTRACE_SETHWDEBUG: {
+ struct ppc_hw_breakpoint bp_info;
+
+ if (!access_ok(VERIFY_READ, data,
+ sizeof(struct ppc_hw_breakpoint)))
+ return -EFAULT;
+ ret = __copy_from_user(&bp_info,
+ (struct ppc_hw_breakpoint __user *)data,
+ sizeof(struct ppc_hw_breakpoint)) ?
+ -EFAULT : 0;
+ if (!ret)
+ ret = ppc_set_hwdebug(child, &bp_info);
+ break;
+ }
+
+ case PPC_PTRACE_DELHWDEBUG: {
+ ret = ppc_del_hwdebug(child, addr, data);
+ break;
+ }
+
case PTRACE_GET_DEBUGREG: {
ret = -EINVAL;
/* We only support one DABR and no IABRS at the moment */
--
Dave Kleikamp
IBM Linux Technology Center
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [RFC:PATCH 03/03] powerpc: Add support for BookE Debug Reg. traps, exceptions and ptrace
2010-01-18 21:57 [RFC:PATCH 00/03] powerpc: Expose BookE debug registers through extended ptrace interface Dave Kleikamp
2010-01-18 21:57 ` [RFC:PATCH 01/03] powerpc: Extended " Dave Kleikamp
@ 2010-01-18 21:57 ` Dave Kleikamp
2010-01-18 21:59 ` [RFC:PATCH 02/03] powerpc: Add definitions for Debug Registers on BookE Platforms Dave Kleikamp
2 siblings, 0 replies; 9+ messages in thread
From: Dave Kleikamp @ 2010-01-18 21:57 UTC (permalink / raw)
To: linuxppc-dev list
Cc: Sergio Durigan Junior, David Gibson, Torez Smith,
Thiago Jung Bauermann
powerpc: Add support for BookE Debug Reg. traps, exceptions and ptrace
From: Torez Smith <lnxtorez@linux.vnet.ibm.com>
This patch defines context switch and trap related functionality
for BookE specific Debug Registers. It adds support to ptrace()
for setting and getting BookE related Debug Registers
Signed-off-by: Torez Smith <lnxtorez@linux.vnet.ibm.com>
Signed-off-by: Dave Kleikamp <shaggy@linux.vnet.ibm.com>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: Josh Boyer <jwboyer@linux.vnet.ibm.com>
Cc: Kumar Gala <galak@kernel.crashing.org>
Cc: Sergio Durigan Junior <sergiodj@br.ibm.com>
Cc: Thiago Jung Bauermann <bauerman@br.ibm.com>
Cc: David Gibson <dwg@au1.ibm.com>
Cc: linuxppc-dev list <Linuxppc-dev@ozlabs.org>
---
arch/powerpc/include/asm/system.h | 5
arch/powerpc/kernel/process.c | 105 +++++++--
arch/powerpc/kernel/ptrace.c | 453 ++++++++++++++++++++++++++++++++++---
arch/powerpc/kernel/signal.c | 6
arch/powerpc/kernel/signal_32.c | 8 -
arch/powerpc/kernel/traps.c | 91 ++++++-
6 files changed, 587 insertions(+), 81 deletions(-)
diff --git a/arch/powerpc/include/asm/system.h b/arch/powerpc/include/asm/system.h
index bb8e006..0634e79 100644
--- a/arch/powerpc/include/asm/system.h
+++ b/arch/powerpc/include/asm/system.h
@@ -112,8 +112,13 @@ static inline int debugger_fault_handler(struct pt_regs *regs) { return 0; }
#endif
extern int set_dabr(unsigned long dabr);
+#if (defined(CONFIG_40x) || defined(CONFIG_BOOKE))
+extern void do_send_trap(struct pt_regs *regs, unsigned long address,
+ unsigned long error_code, int signal_code, int brkpt);
+#else
extern void do_dabr(struct pt_regs *regs, unsigned long address,
unsigned long error_code);
+#endif
extern void print_backtrace(unsigned long *);
extern void show_regs(struct pt_regs * regs);
extern void flush_instruction_cache(void);
diff --git a/arch/powerpc/kernel/process.c b/arch/powerpc/kernel/process.c
index c930ac3..9f4919a 100644
--- a/arch/powerpc/kernel/process.c
+++ b/arch/powerpc/kernel/process.c
@@ -245,6 +245,24 @@ void discard_lazy_cpu_state(void)
}
#endif /* CONFIG_SMP */
+#if (defined(CONFIG_40x) || defined(CONFIG_BOOKE))
+void do_send_trap(struct pt_regs *regs, unsigned long address,
+ unsigned long error_code, int signal_code, int breakpt)
+{
+ siginfo_t info;
+
+ if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code,
+ 11, SIGSEGV) == NOTIFY_STOP)
+ return;
+
+ /* Deliver the signal to userspace */
+ info.si_signo = SIGTRAP;
+ info.si_errno = breakpt; /* breakpoint or watchpoint id */
+ info.si_code = signal_code;
+ info.si_addr = (void __user *)address;
+ force_sig_info(SIGTRAP, &info, current);
+}
+#else /* !(defined(CONFIG_40x) || defined(CONFIG_BOOKE)) */
void do_dabr(struct pt_regs *regs, unsigned long address,
unsigned long error_code)
{
@@ -257,12 +275,6 @@ void do_dabr(struct pt_regs *regs, unsigned long address,
if (debugger_dabr_match(regs))
return;
- /* Clear the DAC and struct entries. One shot trigger */
-#if defined(CONFIG_BOOKE)
- mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~(DBSR_DAC1R | DBSR_DAC1W
- | DBCR0_IDM));
-#endif
-
/* Clear the DABR */
set_dabr(0);
@@ -273,9 +285,73 @@ void do_dabr(struct pt_regs *regs, unsigned long address,
info.si_addr = (void __user *)address;
force_sig_info(SIGTRAP, &info, current);
}
+#endif
static DEFINE_PER_CPU(unsigned long, current_dabr);
+#if defined(CONFIG_BOOKE) || defined(CONFIG_40x)
+/*
+ * Set the debug registers back to their default "safe" values.
+ */
+static void set_debug_reg_defaults(struct thread_struct *thread)
+{
+ thread->iac1 = thread->iac2 = thread->iac3 = thread->iac4 = 0;
+ thread->dac1 = thread->dac2 = 0;
+ thread->dvc1 = thread->dvc2 = 0;
+ thread->dbcr0 = 0;
+#ifdef CONFIG_BOOKE
+ /*
+ * Force User/Supervisor bits to b11 (user-only MSR[PR]=1)
+ */
+ thread->dbcr1 = DBCR1_IAC1US | DBCR1_IAC2US | \
+ DBCR1_IAC3US | DBCR1_IAC4US;
+ /*
+ * Force Data Address Compare User/Supervisor bits to be User-only
+ * (0b11 MSR[PR]=1) and set all other bits in DBCR2 register to be 0.
+ */
+ thread->dbcr2 = DBCR2_DAC1US | DBCR2_DAC2US;
+#else
+ thread->dbcr1 = 0;
+#endif
+}
+
+static void prime_debug_regs(struct thread_struct *thread)
+{
+ mtspr(SPRN_IAC1, thread->iac1);
+ mtspr(SPRN_IAC2, thread->iac2);
+ mtspr(SPRN_IAC3, thread->iac3);
+ mtspr(SPRN_IAC4, thread->iac4);
+ mtspr(SPRN_DAC1, thread->dac1);
+ mtspr(SPRN_DAC2, thread->dac2);
+ mtspr(SPRN_DVC1, thread->dvc1);
+ mtspr(SPRN_DVC2, thread->dvc2);
+ mtspr(SPRN_DBCR0, thread->dbcr0);
+ mtspr(SPRN_DBCR1, thread->dbcr1);
+#ifdef CONFIG_BOOKE
+ mtspr(SPRN_DBCR2, thread->dbcr2);
+#endif
+}
+/*
+ * Unless neither the old or new thread are making use of the
+ * debug registers, set the debug registers from the values
+ * stored in the new thread.
+ */
+static void switch_booke_debug_regs(struct thread_struct *new_thread)
+{
+ if ((current->thread.dbcr0 & DBCR0_IDM)
+ || (new_thread->dbcr0 & DBCR0_IDM))
+ prime_debug_regs(new_thread);
+}
+#else /* !(defined(CONFIG_BOOKE) || defined(CONFIG_40x)) */
+static void set_debug_reg_defaults(struct thread_struct *thread)
+{
+ if (thread->dabr) {
+ thread->dabr = 0;
+ set_dabr(0);
+ }
+}
+#endif
+
int set_dabr(unsigned long dabr)
{
__get_cpu_var(current_dabr) = dabr;
@@ -284,7 +360,7 @@ int set_dabr(unsigned long dabr)
return ppc_md.set_dabr(dabr);
/* XXX should we have a CPU_FTR_HAS_DABR ? */
-#if defined(CONFIG_BOOKE)
+#if defined(CONFIG_BOOKE) || defined(CONFIG_40x)
mtspr(SPRN_DAC1, dabr);
#elif defined(CONFIG_PPC_BOOK3S)
mtspr(SPRN_DABR, dabr);
@@ -371,10 +447,8 @@ struct task_struct *__switch_to(struct task_struct *prev,
#endif /* CONFIG_SMP */
-#if defined(CONFIG_BOOKE)
- /* If new thread DAC (HW breakpoint) is the same then leave it */
- if (new->thread.dabr)
- set_dabr(new->thread.dabr);
+#if defined(CONFIG_BOOKE) || defined(CONFIG_40x)
+ switch_booke_debug_regs(&new->thread);
#else
if (unlikely(__get_cpu_var(current_dabr) != new->thread.dabr))
set_dabr(new->thread.dabr);
@@ -568,14 +642,7 @@ void flush_thread(void)
discard_lazy_cpu_state();
- if (current->thread.dabr) {
- current->thread.dabr = 0;
- set_dabr(0);
-
-#if defined(CONFIG_BOOKE)
- current->thread.dbcr0 &= ~(DBSR_DAC1R | DBSR_DAC1W);
-#endif
- }
+ set_debug_reg_defaults(¤t->thread);
}
void
diff --git a/arch/powerpc/kernel/ptrace.c b/arch/powerpc/kernel/ptrace.c
index 33ab496..d0b74b3 100644
--- a/arch/powerpc/kernel/ptrace.c
+++ b/arch/powerpc/kernel/ptrace.c
@@ -737,17 +737,25 @@ void user_disable_single_step(struct task_struct *task)
struct pt_regs *regs = task->thread.regs;
if (regs != NULL) {
-#if defined(CONFIG_BOOKE)
- /* If DAC don't clear DBCRO_IDM or MSR_DE */
- if (task->thread.dabr)
- task->thread.dbcr0 &= ~(DBCR0_IC | DBCR0_BT);
- else {
- task->thread.dbcr0 &= ~(DBCR0_IC | DBCR0_BT | DBCR0_IDM);
+#if defined(CONFIG_40x) || defined(CONFIG_BOOKE)
+ /*
+ * The logic to disable single stepping should be as
+ * simple as turning off the Instruction Complete flag.
+ * And, after doing so, if all debug flags are off, turn
+ * off DBCR0(IDM) and MSR(DE) .... Torez
+ */
+ task->thread.dbcr0 &= ~DBCR0_IC;
+ /*
+ * Test to see if any of the DBCR_ACTIVE_EVENTS bits are set.
+ */
+ if (!DBCR_ACTIVE_EVENTS(task->thread.dbcr0,
+ task->thread.dbcr1)) {
+ /*
+ * All debug events were off.....
+ */
+ task->thread.dbcr0 &= ~DBCR0_IDM;
regs->msr &= ~MSR_DE;
}
-#elif defined(CONFIG_40x)
- task->thread.dbcr0 &= ~(DBCR0_IC | DBCR0_BT | DBCR0_IDM);
- regs->msr &= ~MSR_DE;
#else
regs->msr &= ~(MSR_SE | MSR_BE);
#endif
@@ -769,8 +777,7 @@ int ptrace_set_debugreg(struct task_struct *task, unsigned long addr,
if ((data & ~0x7UL) >= TASK_SIZE)
return -EIO;
-#ifndef CONFIG_BOOKE
-
+#if !(defined(CONFIG_40x) || defined(CONFIG_BOOKE))
/* For processors using DABR (i.e. 970), the bottom 3 bits are flags.
* It was assumed, on previous implementations, that 3 bits were
* passed together with the data address, fitting the design of the
@@ -789,21 +796,22 @@ int ptrace_set_debugreg(struct task_struct *task, unsigned long addr,
/* Move contents to the DABR register */
task->thread.dabr = data;
-
-#endif
-#if defined(CONFIG_BOOKE)
-
+#else
/* As described above, it was assumed 3 bits were passed with the data
* address, but we will assume only the mode bits will be passed
* as to not cause alignment restrictions for DAC-based processors.
*/
/* DAC's hold the whole address without any mode flags */
- task->thread.dabr = data & ~0x3UL;
-
- if (task->thread.dabr == 0) {
- task->thread.dbcr0 &= ~(DBSR_DAC1R | DBSR_DAC1W | DBCR0_IDM);
- task->thread.regs->msr &= ~MSR_DE;
+ task->thread.dac1 = data & ~0x3UL;
+
+ if (task->thread.dac1 == 0) {
+ dbcr_dac(task) &= ~(DBCR_DAC1R | DBCR_DAC1W);
+ if (!DBCR_ACTIVE_EVENTS(task->thread.dbcr0,
+ task->thread.dbcr1)) {
+ task->thread.regs->msr &= ~MSR_DE;
+ task->thread.dbcr0 &= ~DBCR0_IDM;
+ }
return 0;
}
@@ -814,15 +822,15 @@ int ptrace_set_debugreg(struct task_struct *task, unsigned long addr,
/* Set the Internal Debugging flag (IDM bit 1) for the DBCR0
register */
- task->thread.dbcr0 = DBCR0_IDM;
+ task->thread.dbcr0 |= DBCR0_IDM;
/* Check for write and read flags and set DBCR0
accordingly */
+ dbcr_dac(task) &= ~(DBCR_DAC1R|DBCR_DAC1W);
if (data & 0x1UL)
- task->thread.dbcr0 |= DBSR_DAC1R;
+ dbcr_dac(task) |= DBCR_DAC1R;
if (data & 0x2UL)
- task->thread.dbcr0 |= DBSR_DAC1W;
-
+ dbcr_dac(task) |= DBCR_DAC1W;
task->thread.regs->msr |= MSR_DE;
#endif
return 0;
@@ -839,11 +847,346 @@ void ptrace_disable(struct task_struct *child)
user_disable_single_step(child);
}
+#if defined(CONFIG_40x) || defined(CONFIG_BOOKE)
+static long set_intruction_bp(struct task_struct *child,
+ struct ppc_hw_breakpoint *bp_info)
+{
+ int slot;
+ int slot1_in_use = ((child->thread.dbcr0 & DBCR0_IAC1) != 0);
+ int slot2_in_use = ((child->thread.dbcr0 & DBCR0_IAC2) != 0);
+ int slot3_in_use = ((child->thread.dbcr0 & DBCR0_IAC3) != 0);
+ int slot4_in_use = ((child->thread.dbcr0 & DBCR0_IAC4) != 0);
+
+ if (dbcr_iac_range(child) & DBCR_IAC12MODE)
+ slot2_in_use = 1;
+ if (dbcr_iac_range(child) & DBCR_IAC34MODE)
+ slot4_in_use = 1;
+
+ if (bp_info->addr >= TASK_SIZE)
+ return -EIO;
+
+ if (bp_info->addr_mode != PPC_BREAKPOINT_MODE_EXACT) {
+
+ /* Make sure range is valid. */
+ if (bp_info->addr2 >= TASK_SIZE)
+ return -EIO;
+
+ /* We need a pair of IAC regsisters */
+ if ((!slot1_in_use) && (!slot2_in_use)) {
+ slot = 1;
+ child->thread.iac1 = bp_info->addr;
+ child->thread.iac2 = bp_info->addr2;
+ child->thread.dbcr0 |= DBCR0_IAC1;
+ if (bp_info->addr_mode ==
+ PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE)
+ dbcr_iac_range(child) |= DBCR_IAC12X;
+ else
+ dbcr_iac_range(child) |= DBCR_IAC12I;
+ } else if ((!slot3_in_use) && (!slot4_in_use)) {
+ slot = 3;
+ child->thread.iac3 = bp_info->addr;
+ child->thread.iac4 = bp_info->addr2;
+ child->thread.dbcr0 |= DBCR0_IAC3;
+ if (bp_info->addr_mode ==
+ PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE)
+ dbcr_iac_range(child) |= DBCR_IAC34X;
+ else
+ dbcr_iac_range(child) |= DBCR_IAC34I;
+ } else
+ return -ENOSPC;
+ } else {
+ /* We only need one. If possible leave a pair free in
+ * case a range is needed later
+ */
+ if (!slot1_in_use) {
+ /*
+ * Don't use iac1 if iac1-iac2 are free and either
+ * iac3 or iac4 (but not both) are free
+ */
+ if (slot2_in_use || (slot3_in_use == slot4_in_use)) {
+ slot = 1;
+ child->thread.iac1 = bp_info->addr;
+ child->thread.dbcr0 |= DBCR0_IAC1;
+ goto out;
+ }
+ }
+ if (!slot2_in_use) {
+ slot = 2;
+ child->thread.iac2 = bp_info->addr;
+ child->thread.dbcr0 |= DBCR0_IAC2;
+ } else if (!slot3_in_use) {
+ slot = 3;
+ child->thread.iac3 = bp_info->addr;
+ child->thread.dbcr0 |= DBCR0_IAC3;
+ } else if (!slot4_in_use) {
+ slot = 4;
+ child->thread.iac4 = bp_info->addr;
+ child->thread.dbcr0 |= DBCR0_IAC4;
+ } else
+ return -ENOSPC;
+ }
+out:
+ child->thread.dbcr0 |= DBCR0_IDM;
+ child->thread.regs->msr |= MSR_DE;
+
+ return slot;
+}
+
+static int del_instruction_bp(struct task_struct *child, int slot)
+{
+ switch (slot) {
+ case 1:
+ if (child->thread.iac1 == 0)
+ return -ENOENT;
+
+ if (dbcr_iac_range(child) & DBCR_IAC12MODE) {
+ /* address range - clear slots 1 & 2 */
+ child->thread.iac2 = 0;
+ dbcr_iac_range(child) &= ~DBCR_IAC12MODE;
+ }
+ child->thread.iac1 = 0;
+ child->thread.dbcr0 &= ~DBCR0_IAC1;
+ break;
+ case 2:
+ if (child->thread.iac2 == 0)
+ return -ENOENT;
+
+ if (dbcr_iac_range(child) & DBCR_IAC12MODE)
+ /* used in a range */
+ return -EINVAL;
+ child->thread.iac2 = 0;
+ child->thread.dbcr0 &= ~DBCR0_IAC2;
+ break;
+ case 3:
+ if (child->thread.iac3 == 0)
+ return -ENOENT;
+
+ if (dbcr_iac_range(child) & DBCR_IAC34MODE) {
+ /* address range - clear slots 3 & 4 */
+ child->thread.iac4 = 0;
+ dbcr_iac_range(child) &= ~DBCR_IAC34MODE;
+ }
+ child->thread.iac3 = 0;
+ child->thread.dbcr0 &= ~DBCR0_IAC3;
+ break;
+ case 4:
+ if (child->thread.iac4 == 0)
+ return -ENOENT;
+
+ if (dbcr_iac_range(child) & DBCR_IAC34MODE)
+ /* Used in a range */
+ return -EINVAL;
+ child->thread.iac4 = 0;
+ child->thread.dbcr0 &= ~DBCR0_IAC4;
+ break;
+ default:
+ return -EINVAL;
+ }
+ return 0;
+}
+
+static int set_dac(struct task_struct *child, struct ppc_hw_breakpoint *bp_info)
+{
+ int byte_enable =
+ (bp_info->condition_mode >> PPC_BREAKPOINT_CONDITION_BE_SHIFT)
+ & 0xf;
+ int condition_mode =
+ bp_info->condition_mode & PPC_BREAKPOINT_CONDITION_MODE;
+ int slot;
+
+ if (byte_enable && (condition_mode == 0))
+ return -EINVAL;
+
+ if (bp_info->addr >= TASK_SIZE)
+ return -EIO;
+
+ if ((dbcr_dac(child) & (DBCR_DAC1R | DBCR_DAC1W)) == 0) {
+ slot = 1;
+ if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_READ)
+ dbcr_dac(child) |= DBCR_DAC1R;
+ if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_WRITE)
+ dbcr_dac(child) |= DBCR_DAC1W;
+ child->thread.dac1 = (unsigned long)bp_info->addr;
+#ifdef CONFIG_BOOKE
+ if (byte_enable) {
+ child->thread.dvc1 =
+ (unsigned long)bp_info->condition_value;
+ child->thread.dbcr2 |=
+ ((byte_enable << DBCR2_DVC1BE_SHIFT) |
+ (condition_mode << DBCR2_DVC1M_SHIFT));
+ }
+ } else if (child->thread.dbcr2 & DBCR2_DAC12MODE) {
+ /* Both dac1 and dac2 are part of a range */
+ return -ENOSPC;
+#endif
+ } else if ((dbcr_dac(child) & (DBCR_DAC2R | DBCR_DAC2W)) == 0) {
+ slot = 2;
+ if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_READ)
+ dbcr_dac(child) |= DBCR_DAC2R;
+ if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_WRITE)
+ dbcr_dac(child) |= DBCR_DAC2W;
+ child->thread.dac2 = (unsigned long)bp_info->addr;
+#ifdef CONFIG_BOOKE
+ if (byte_enable) {
+ child->thread.dvc2 =
+ (unsigned long)bp_info->condition_value;
+ child->thread.dbcr2 |=
+ ((byte_enable << DBCR2_DVC2BE_SHIFT) |
+ (condition_mode << DBCR2_DVC2M_SHIFT));
+ }
+#endif
+ } else
+ return -ENOSPC;
+ child->thread.dbcr0 |= DBCR0_IDM;
+ child->thread.regs->msr |= MSR_DE;
+
+ return slot + 4;
+}
+
+static int del_dac(struct task_struct *child, int slot)
+{
+ if (slot == 1) {
+ if (child->thread.dac1 == 0)
+ return -ENOENT;
+
+ child->thread.dac1 = 0;
+ dbcr_dac(child) &= ~(DBCR_DAC1R | DBCR_DAC1W);
+#ifdef CONFIG_BOOKE
+ if (child->thread.dbcr2 & DBCR2_DAC12MODE) {
+ child->thread.dac2 = 0;
+ child->thread.dbcr2 &= ~DBCR2_DAC12MODE;
+ }
+ child->thread.dbcr2 &= ~(DBCR2_DVC1M | DBCR2_DVC1BE);
+#endif
+ child->thread.dvc1 = 0;
+ } else if (slot == 2) {
+ if (child->thread.dac1 == 0)
+ return -ENOENT;
+
+#ifdef CONFIG_BOOKE
+ if (child->thread.dbcr2 & DBCR2_DAC12MODE)
+ /* Part of a range */
+ return -EINVAL;
+ child->thread.dbcr2 &= ~(DBCR2_DVC2M | DBCR2_DVC2BE);
+#endif
+ child->thread.dvc2 = 0;
+ child->thread.dac2 = 0;
+ dbcr_dac(child) &= ~(DBCR_DAC2R | DBCR_DAC2W);
+ } else
+ return -EINVAL;
+
+ return 0;
+}
+#endif /* CONFIG_40x || CONFIG_BOOKE */
+
+#ifdef CONFIG_BOOKE
+static int set_dac_range(struct task_struct *child,
+ struct ppc_hw_breakpoint *bp_info)
+{
+ int mode = bp_info->addr_mode & PPC_BREAKPOINT_MODE_MASK;
+
+ /* We don't allow range watchpoints to be used with DVC */
+ if (bp_info->condition_mode)
+ return -EINVAL;
+
+ if (bp_info->addr >= TASK_SIZE)
+ return -EIO;
+ if (mode == PPC_BREAKPOINT_MODE_MASK) {
+ /*
+ * dac2 is a bitmask. Don't allow a mask that makes a
+ * kernel space address from a valid dac1 value
+ */
+ if (~bp_info->addr2 >= TASK_SIZE)
+ return -EIO;
+ } else {
+ /*
+ * For range breakpoints, addr2 must also be a valid address
+ *
+ * XXX - How do we protect kernel space when in range exclusive
+ * mode? bookE will only trap in user mode, but what about
+ * 405?
+ */
+ if (bp_info->addr >= TASK_SIZE)
+ return -EIO;
+ }
+
+
+ if (child->thread.dbcr0 &
+ (DBCR0_DAC1R | DBCR0_DAC1W | DBCR0_DAC2R | DBCR0_DAC2W))
+ return -ENOSPC;
+
+ if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_READ)
+ child->thread.dbcr0 |= (DBCR0_DAC1R | DBCR0_IDM);
+ if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_WRITE)
+ child->thread.dbcr0 |= (DBCR0_DAC1W | DBCR0_IDM);
+ child->thread.dac1 = bp_info->addr;
+ child->thread.dac2 = bp_info->addr2;
+ if (mode == PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE)
+ child->thread.dbcr2 |= DBCR2_DAC12M;
+ else if (mode == PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE)
+ child->thread.dbcr2 |= DBCR2_DAC12MX;
+ else /* PPC_BREAKPOINT_MODE_MASK */
+ child->thread.dbcr2 |= DBCR2_DAC12MM;
+ child->thread.regs->msr |= MSR_DE;
+
+ return 5;
+}
+#endif /* CONFIG_BOOKE */
+
static long ppc_set_hwdebug(struct task_struct *child,
struct ppc_hw_breakpoint *bp_info)
{
+ if (bp_info->version != 1)
+ return -ENOTSUPP;
+
+#ifdef CONFIG_BOOKE
+ /*
+ * Check for invalid flags and combinations
+ */
+ if ((bp_info->trigger_type == 0) ||
+ (bp_info->trigger_type & ~(PPC_BREAKPOINT_TRIGGER_EXECUTE |
+ PPC_BREAKPOINT_TRIGGER_RW)) ||
+ (bp_info->addr_mode & ~PPC_BREAKPOINT_MODE_MASK) ||
+ (bp_info->condition_mode &
+ ~(PPC_BREAKPOINT_CONDITION_MODE |
+ PPC_BREAKPOINT_CONDITION_BE_ALL)))
+ return -EINVAL;
+
+ if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_EXECUTE) {
+ if (bp_info->trigger_type != PPC_BREAKPOINT_TRIGGER_EXECUTE)
+ /* At least another bit was set */
+ return -EINVAL;
+ return set_intruction_bp(child, bp_info);
+ }
+
+ if (bp_info->addr_mode == PPC_BREAKPOINT_MODE_EXACT)
+ return set_dac(child, bp_info);
+
+ return set_dac_range(child, bp_info);
+#elif defined(CONFIG_40x)
+ /*
+ * Check for invalid flags and combinations
+ */
+ if ((bp_info->trigger_type == 0) ||
+ (bp_info->trigger_type & ~(PPC_BREAKPOINT_TRIGGER_EXECUTE |
+ PPC_BREAKPOINT_TRIGGER_RW)) ||
+ (bp_info->addr_mode & ~PPC_BREAKPOINT_MODE_MASK) ||
+ (bp_info->condition_mode != PPC_BREAKPOINT_CONDITION_NONE))
+ return -EINVAL;
+
+ if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_EXECUTE) {
+ if (bp_info->trigger_type != PPC_BREAKPOINT_TRIGGER_EXECUTE)
+ /* At least another bit was set */
+ return -EINVAL;
+ return set_intruction_bp(child, bp_info);
+ }
+ if (bp_info->addr_mode != PPC_BREAKPOINT_MODE_EXACT)
+ return -EINVAL;
+
+ return set_dac(child, bp_info);
+#else
/*
- * We currently support one data breakpoint
+ * We only support one data breakpoint
*/
if (((bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_RW) == 0) ||
((bp_info->trigger_type & ~PPC_BREAKPOINT_TRIGGER_RW) != 0) ||
@@ -859,30 +1202,37 @@ static long ppc_set_hwdebug(struct task_struct *child,
return -EIO;
child->thread.dabr = (unsigned long)bp_info->addr;
-#ifdef CONFIG_BOOKE
- child->thread.dbcr0 = DBCR0_IDM;
- if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_READ)
- child->thread.dbcr0 |= DBSR_DAC1R;
- if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_WRITE)
- child->thread.dbcr0 |= DBSR_DAC1W;
- child->thread.regs->msr |= MSR_DE;
-#endif
return 1;
+#endif
}
static long ppc_del_hwdebug(struct task_struct *child, long addr, long data)
{
+#if defined(CONFIG_40x) || defined(CONFIG_BOOKE)
+ int rc;
+
+ if (data <= 4)
+ rc = del_instruction_bp(child, (int)data);
+ else
+ rc = del_dac(child, (int)data - 4);
+
+ if (!rc) {
+ if (!DBCR_ACTIVE_EVENTS(child->thread.dbcr0,
+ child->thread.dbcr1)) {
+ child->thread.dbcr0 &= ~DBCR0_IDM;
+ child->thread.regs->msr &= ~MSR_DE;
+ }
+ }
+ return rc;
+#else
if (data != 1)
return -EINVAL;
if (child->thread.dabr == 0)
return -ENOENT;
child->thread.dabr = 0;
-#ifdef CONFIG_BOOKE
- child->thread.dbcr0 &= ~(DBSR_DAC1R | DBSR_DAC1W | DBCR0_IDM);
- child->thread.regs->msr &= ~MSR_DE;
-#endif
return 0;
+#endif
}
/*
@@ -982,6 +1332,29 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data)
struct ppc_debug_info dbginfo;
dbginfo.version = 1;
+#ifdef CONFIG_BOOKE
+ dbginfo.num_instruction_bps = 4;
+ dbginfo.num_data_bps = 2;
+ dbginfo.num_condition_regs = 2;
+ dbginfo.data_bp_alignment = 4;
+ dbginfo.sizeof_condition = 4;
+ dbginfo.features = PPC_DEBUG_FEATURE_INSN_BP_RANGE |
+ PPC_DEBUG_FEATURE_INSN_BP_MASK |
+ PPC_DEBUG_FEATURE_DATA_BP_RANGE |
+ PPC_DEBUG_FEATURE_DATA_BP_MASK;
+#elif defined(CONFIG_40x)
+ /*
+ * I don't know how the DVCs work on 40x, I'm not going
+ * to support it now. -- Shaggy
+ */
+ dbginfo.num_instruction_bps = 4;
+ dbginfo.num_data_bps = 2;
+ dbginfo.num_condition_regs = 0;
+ dbginfo.data_bp_alignment = 4;
+ dbginfo.sizeof_condition = 0;
+ dbginfo.features = PPC_DEBUG_FEATURE_INSN_BP_RANGE |
+ PPC_DEBUG_FEATURE_INSN_BP_MASK;
+#else
dbginfo.num_instruction_bps = 0;
dbginfo.num_data_bps = 1;
dbginfo.num_condition_regs = 0;
@@ -992,6 +1365,7 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data)
#endif
dbginfo.sizeof_condition = 0;
dbginfo.features = 0;
+#endif
if (!access_ok(VERIFY_WRITE, data,
sizeof(struct ppc_debug_info)))
@@ -1027,8 +1401,13 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data)
/* We only support one DABR and no IABRS at the moment */
if (addr > 0)
break;
+#if defined(CONFIG_40x) || defined(CONFIG_BOOKE)
+ ret = put_user(child->thread.dac1,
+ (unsigned long __user *)data);
+#else
ret = put_user(child->thread.dabr,
(unsigned long __user *)data);
+#endif
break;
}
diff --git a/arch/powerpc/kernel/signal.c b/arch/powerpc/kernel/signal.c
index 00b5078..94df779 100644
--- a/arch/powerpc/kernel/signal.c
+++ b/arch/powerpc/kernel/signal.c
@@ -140,17 +140,15 @@ static int do_signal_pending(sigset_t *oldset, struct pt_regs *regs)
return 0; /* no signals delivered */
}
+#if !(defined(CONFIG_BOOKE) || defined(CONFIG_40x))
/*
* Reenable the DABR before delivering the signal to
* user space. The DABR will have been cleared if it
* triggered inside the kernel.
*/
- if (current->thread.dabr) {
+ if (current->thread.dabr)
set_dabr(current->thread.dabr);
-#if defined(CONFIG_BOOKE)
- mtspr(SPRN_DBCR0, current->thread.dbcr0);
#endif
- }
if (is32) {
if (ka.sa.sa_flags & SA_SIGINFO)
diff --git a/arch/powerpc/kernel/signal_32.c b/arch/powerpc/kernel/signal_32.c
index d670429..6cc6e81 100644
--- a/arch/powerpc/kernel/signal_32.c
+++ b/arch/powerpc/kernel/signal_32.c
@@ -1092,8 +1092,12 @@ int sys_debug_setcontext(struct ucontext __user *ctx,
new_msr |= MSR_DE;
new_dbcr0 |= (DBCR0_IDM | DBCR0_IC);
} else {
- new_msr &= ~MSR_DE;
- new_dbcr0 &= ~(DBCR0_IDM | DBCR0_IC);
+ new_dbcr0 &= ~DBCR0_IC;
+ if (!DBCR_ACTIVE_EVENTS(new_dbcr0,
+ current->thread.dbcr1)) {
+ new_msr &= ~MSR_DE;
+ new_dbcr0 &= ~DBCR0_IDM;
+ }
}
#else
if (op.dbg_value)
diff --git a/arch/powerpc/kernel/traps.c b/arch/powerpc/kernel/traps.c
index d069ff8..49dc5fa 100644
--- a/arch/powerpc/kernel/traps.c
+++ b/arch/powerpc/kernel/traps.c
@@ -1025,9 +1025,68 @@ void SoftwareEmulation(struct pt_regs *regs)
#endif /* CONFIG_8xx */
#if defined(CONFIG_40x) || defined(CONFIG_BOOKE)
+static void handle_debug(struct pt_regs *regs, unsigned long debug_status)
+{
+ int changed = 0;
+ /*
+ * Determine the cause of the debug event, clear the
+ * event flags and send a trap to the handler. Torez
+ */
+ if (debug_status & (DBSR_DAC1R | DBSR_DAC1W)) {
+ dbcr_dac(current) &= ~(DBCR_DAC1R | DBCR_DAC1W);
+#ifdef CONFIG_BOOKE
+ current->thread.dbcr2 &= ~DBCR2_DAC12MODE;
+#endif
+ do_send_trap(regs, mfspr(SPRN_DAC1), debug_status, TRAP_HWBKPT,
+ 5);
+ changed |= 0x01;
+ } else if (debug_status & (DBSR_DAC2R | DBSR_DAC2W)) {
+ dbcr_dac(current) &= ~(DBCR_DAC2R | DBCR_DAC2W);
+ do_send_trap(regs, mfspr(SPRN_DAC2), debug_status, TRAP_HWBKPT,
+ 6);
+ changed |= 0x01;
+ } else if (debug_status & DBSR_IAC1) {
+ current->thread.dbcr0 &= ~DBCR0_IAC1;
+ dbcr_iac_range(current) &= ~DBCR_IAC12MODE;
+ do_send_trap(regs, mfspr(SPRN_IAC1), debug_status, TRAP_HWBKPT,
+ 1);
+ changed |= 0x01;
+ } else if (debug_status & DBSR_IAC2) {
+ current->thread.dbcr0 &= ~DBCR0_IAC2;
+ do_send_trap(regs, mfspr(SPRN_IAC2), debug_status, TRAP_HWBKPT,
+ 2);
+ changed |= 0x01;
+ } else if (debug_status & DBSR_IAC3) {
+ current->thread.dbcr0 &= ~DBCR0_IAC3;
+ dbcr_iac_range(current) &= ~DBCR_IAC34MODE;
+ do_send_trap(regs, mfspr(SPRN_IAC3), debug_status, TRAP_HWBKPT,
+ 3);
+ changed |= 0x01;
+ } else if (debug_status & DBSR_IAC4) {
+ current->thread.dbcr0 &= ~DBCR0_IAC4;
+ do_send_trap(regs, mfspr(SPRN_IAC4), debug_status, TRAP_HWBKPT,
+ 4);
+ changed |= 0x01;
+ }
+ /*
+ * At the point this routine was called, the MSR(DE) was turned off.
+ * Check all other debug flags and see if that bit needs to be turned
+ * back on or not.
+ */
+ if (DBCR_ACTIVE_EVENTS(current->thread.dbcr0, current->thread.dbcr1))
+ regs->msr |= MSR_DE;
+ else
+ /* Make sure the IDM flag is off */
+ current->thread.dbcr0 &= ~DBCR0_IDM;
+
+ if (changed & 0x01)
+ mtspr(SPRN_DBCR0, current->thread.dbcr0);
+}
void __kprobes DebugException(struct pt_regs *regs, unsigned long debug_status)
{
+ current->thread.dbsr = debug_status;
+
/* Hack alert: On BookE, Branch Taken stops on the branch itself, while
* on server, it stops on the target of the branch. In order to simulate
* the server behaviour, we thus restart right away with a single step
@@ -1071,27 +1130,21 @@ void __kprobes DebugException(struct pt_regs *regs, unsigned long debug_status)
if (debugger_sstep(regs))
return;
- if (user_mode(regs))
- current->thread.dbcr0 &= ~(DBCR0_IC);
-
- _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip);
- } else if (debug_status & (DBSR_DAC1R | DBSR_DAC1W)) {
- regs->msr &= ~MSR_DE;
-
if (user_mode(regs)) {
- current->thread.dbcr0 &= ~(DBSR_DAC1R | DBSR_DAC1W |
- DBCR0_IDM);
- } else {
- /* Disable DAC interupts */
- mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~(DBSR_DAC1R |
- DBSR_DAC1W | DBCR0_IDM));
-
- /* Clear the DAC event */
- mtspr(SPRN_DBSR, (DBSR_DAC1R | DBSR_DAC1W));
+ current->thread.dbcr0 &= ~DBCR0_IC;
+#if defined(CONFIG_40x) || defined(CONFIG_BOOKE)
+ if (DBCR_ACTIVE_EVENTS(current->thread.dbcr0,
+ current->thread.dbcr1))
+ regs->msr |= MSR_DE;
+ else
+ /* Make sure the IDM bit is off */
+ current->thread.dbcr0 &= ~DBCR0_IDM;
+#endif
}
- /* Setup and send the trap to the handler */
- do_dabr(regs, mfspr(SPRN_DAC1), debug_status);
- }
+
+ _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip);
+ } else
+ handle_debug(regs, debug_status);
}
#endif /* CONFIG_4xx || CONFIG_BOOKE */
--
Dave Kleikamp
IBM Linux Technology Center
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [RFC:PATCH 02/03] powerpc: Add definitions for Debug Registers on BookE Platforms
2010-01-18 21:57 [RFC:PATCH 00/03] powerpc: Expose BookE debug registers through extended ptrace interface Dave Kleikamp
2010-01-18 21:57 ` [RFC:PATCH 01/03] powerpc: Extended " Dave Kleikamp
2010-01-18 21:57 ` [RFC:PATCH 03/03] powerpc: Add support for BookE Debug Reg. traps, exceptions and ptrace Dave Kleikamp
@ 2010-01-18 21:59 ` Dave Kleikamp
2 siblings, 0 replies; 9+ messages in thread
From: Dave Kleikamp @ 2010-01-18 21:59 UTC (permalink / raw)
To: linuxppc-dev list
Cc: Sergio Durigan Junior, David Gibson, Torez Smith,
Thiago Jung Bauermann
powerpc: Add definitions for Debug Registers on BookE Platforms
From: Torez Smith <lnxtorez@linux.vnet.ibm.com>
This patch adds additional definitions for BookE Debug Registers
to the reg_booke.h header file.
Signed-off-by: Torez Smith <lnxtorez@linux.vnet.ibm.com>
Signed-off-by: Dave Kleikamp <shaggy@linux.vnet.ibm.com>
Acked-by: David Gibson <dwg@au1.ibm.com>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: Josh Boyer <jwboyer@linux.vnet.ibm.com>
Cc: Kumar Gala <galak@kernel.crashing.org>
Cc: Sergio Durigan Junior <sergiodj@br.ibm.com>
Cc: Thiago Jung Bauermann <bauerman@br.ibm.com>
Cc: linuxppc-dev list <Linuxppc-dev@ozlabs.org>
---
arch/powerpc/include/asm/processor.h | 32 +++++++++++
arch/powerpc/include/asm/reg_booke.h | 96 ++++++++++++++++++++++++++++++++++
2 files changed, 125 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h
index 9eed29e..ab0ee94 100644
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@@ -161,9 +161,37 @@ struct thread_struct {
#ifdef CONFIG_PPC32
void *pgdir; /* root of page-table tree */
#endif
-#if defined(CONFIG_4xx) || defined (CONFIG_BOOKE)
- unsigned long dbcr0; /* debug control register values */
+#if defined(CONFIG_40x) || defined(CONFIG_BOOKE)
+ /*
+ * The following help to manage the use of Debug Control Registers
+ * om the BookE platforms.
+ */
+ unsigned long dbcr0;
unsigned long dbcr1;
+#ifdef CONFIG_BOOKE
+ unsigned long dbcr2;
+#endif
+ /*
+ * The stored value of the DBSR register will be the value at the
+ * last debug interrupt. This register can only be read from the
+ * user (will never be written to) and has value while helping to
+ * describe the reason for the last debug trap. Torez
+ */
+ unsigned long dbsr;
+ /*
+ * The following will contain addresses used by debug applications
+ * to help trace and trap on particular address locations.
+ * The bits in the Debug Control Registers above help define which
+ * of the following registers will contain valid data and/or addresses.
+ */
+ unsigned long iac1;
+ unsigned long iac2;
+ unsigned long iac3;
+ unsigned long iac4;
+ unsigned long dac1;
+ unsigned long dac2;
+ unsigned long dvc1;
+ unsigned long dvc2;
#endif
/* FP and VSX 0-31 register set */
double fpr[32][TS_FPRWIDTH];
diff --git a/arch/powerpc/include/asm/reg_booke.h b/arch/powerpc/include/asm/reg_booke.h
index 3bf7835..8808d30 100644
--- a/arch/powerpc/include/asm/reg_booke.h
+++ b/arch/powerpc/include/asm/reg_booke.h
@@ -248,6 +248,8 @@
#define DBSR_RET 0x00008000 /* Return Debug Event */
#define DBSR_CIRPT 0x00000040 /* Critical Interrupt Taken Event */
#define DBSR_CRET 0x00000020 /* Critical Return Debug Event */
+#define DBSR_IAC12ATS 0x00000002 /* Instr Address Compare 1/2 Toggle */
+#define DBSR_IAC34ATS 0x00000001 /* Instr Address Compare 3/4 Toggle */
#endif
#ifdef CONFIG_40x
#define DBSR_IC 0x80000000 /* Instruction Completion */
@@ -313,6 +315,38 @@
#define DBCR0_IA12T 0x00008000 /* Instr Addr 1-2 range Toggle */
#define DBCR0_IA34T 0x00004000 /* Instr Addr 3-4 range Toggle */
#define DBCR0_FT 0x00000001 /* Freeze Timers on debug event */
+
+#define dbcr_iac_range(task) ((task)->thread.dbcr0)
+#define DBCR_IAC12I DBCR0_IA12 /* Range Inclusive */
+#define DBCR_IAC12X (DBCR0_IA12 | DBCR0_IA12X) /* Range Exclusive */
+#define DBCR_IAC12MODE (DBCR0_IA12 | DBCR0_IA12X) /* IAC 1-2 Mode Bits */
+#define DBCR_IAC34I DBCR0_IA34 /* Range Inclusive */
+#define DBCR_IAC34X (DBCR0_IA34 | DBCR0_IA34X) /* Range Exclusive */
+#define DBCR_IAC34MODE (DBCR0_IA34 | DBCR0_IA34X) /* IAC 3-4 Mode Bits */
+
+/* Bit definitions related to the DBCR1. */
+#define DBCR1_DAC1R 0x80000000 /* DAC1 Read Debug Event */
+#define DBCR1_DAC2R 0x40000000 /* DAC2 Read Debug Event */
+#define DBCR1_DAC1W 0x20000000 /* DAC1 Write Debug Event */
+#define DBCR1_DAC2W 0x10000000 /* DAC2 Write Debug Event */
+
+#define dbcr_dac(task) ((task)->thread.dbcr1)
+#define DBCR_DAC1R DBCR1_DAC1R
+#define DBCR_DAC1W DBCR1_DAC1W
+#define DBCR_DAC2R DBCR1_DAC2R
+#define DBCR_DAC2W DBCR1_DAC2W
+
+/*
+ * Are there any active Debug Events represented in the
+ * Debug Control Registers?
+ */
+#define DBCR0_ACTIVE_EVENTS (DBCR0_ICMP | DBCR0_IAC1 | DBCR0_IAC2 | \
+ DBCR0_IAC3 | DBCR0_IAC4)
+#define DBCR1_ACTIVE_EVENTS (DBCR1_DAC1R | DBCR1_DAC2R | \
+ DBCR1_DAC1W | DBCR1_DAC2W)
+#define DBCR_ACTIVE_EVENTS(dbcr0, dbcr1) (((dbcr0) & DBCR0_ACTIVE_EVENTS) || \
+ ((dbcr1) & DBCR1_ACTIVE_EVENTS))
+
#elif defined(CONFIG_BOOKE)
#define DBCR0_EDM 0x80000000 /* External Debug Mode */
#define DBCR0_IDM 0x40000000 /* Internal Debug Mode */
@@ -342,19 +376,79 @@
#define DBCR0_CRET 0x00000020 /* Critical Return Debug Event */
#define DBCR0_FT 0x00000001 /* Freeze Timers on debug event */
+#define dbcr_dac(task) ((task)->thread.dbcr0)
+#define DBCR_DAC1R DBCR0_DAC1R
+#define DBCR_DAC1W DBCR0_DAC1W
+#define DBCR_DAC2R DBCR0_DAC2R
+#define DBCR_DAC2W DBCR0_DAC2W
+
/* Bit definitions related to the DBCR1. */
+#define DBCR1_IAC1US 0xC0000000 /* Instr Addr Cmp 1 Sup/User */
+#define DBCR1_IAC1ER 0x30000000 /* Instr Addr Cmp 1 Eff/Real */
+#define DBCR1_IAC1ER_01 0x10000000 /* reserved */
+#define DBCR1_IAC1ER_10 0x20000000 /* Instr Addr Cmp 1 Eff/Real MSR[IS]=0 */
+#define DBCR1_IAC1ER_11 0x30000000 /* Instr Addr Cmp 1 Eff/Real MSR[IS]=1 */
+#define DBCR1_IAC2US 0x0C000000 /* Instr Addr Cmp 2 Sup/User */
+#define DBCR1_IAC2ER 0x03000000 /* Instr Addr Cmp 2 Eff/Real */
+#define DBCR1_IAC2ER_01 0x01000000 /* reserved */
+#define DBCR1_IAC2ER_10 0x02000000 /* Instr Addr Cmp 2 Eff/Real MSR[IS]=0 */
+#define DBCR1_IAC2ER_11 0x03000000 /* Instr Addr Cmp 2 Eff/Real MSR[IS]=1 */
#define DBCR1_IAC12M 0x00800000 /* Instr Addr 1-2 range enable */
#define DBCR1_IAC12MX 0x00C00000 /* Instr Addr 1-2 range eXclusive */
#define DBCR1_IAC12AT 0x00010000 /* Instr Addr 1-2 range Toggle */
+#define DBCR1_IAC3US 0x0000C000 /* Instr Addr Cmp 3 Sup/User */
+#define DBCR1_IAC3ER 0x00003000 /* Instr Addr Cmp 3 Eff/Real */
+#define DBCR1_IAC3ER_01 0x00001000 /* reserved */
+#define DBCR1_IAC3ER_10 0x00002000 /* Instr Addr Cmp 3 Eff/Real MSR[IS]=0 */
+#define DBCR1_IAC3ER_11 0x00003000 /* Instr Addr Cmp 3 Eff/Real MSR[IS]=1 */
+#define DBCR1_IAC4US 0x00000C00 /* Instr Addr Cmp 4 Sup/User */
+#define DBCR1_IAC4ER 0x00000300 /* Instr Addr Cmp 4 Eff/Real */
+#define DBCR1_IAC4ER_01 0x00000100 /* Instr Addr Cmp 4 Eff/Real MSR[IS]=0 */
+#define DBCR1_IAC4ER_10 0x00000200 /* Instr Addr Cmp 4 Eff/Real MSR[IS]=0 */
+#define DBCR1_IAC4ER_11 0x00000300 /* Instr Addr Cmp 4 Eff/Real MSR[IS]=1 */
#define DBCR1_IAC34M 0x00000080 /* Instr Addr 3-4 range enable */
#define DBCR1_IAC34MX 0x000000C0 /* Instr Addr 3-4 range eXclusive */
#define DBCR1_IAC34AT 0x00000001 /* Instr Addr 3-4 range Toggle */
+#define dbcr_iac_range(task) ((task)->thread.dbcr1)
+#define DBCR_IAC12I DBCR1_IAC12M /* Range Inclusive */
+#define DBCR_IAC12X DBCR1_IAC12MX /* Range Exclusive */
+#define DBCR_IAC12MODE DBCR1_IAC12MX /* IAC 1-2 Mode Bits */
+#define DBCR_IAC34I DBCR1_IAC34M /* Range Inclusive */
+#define DBCR_IAC34X DBCR1_IAC34MX /* Range Exclusive */
+#define DBCR_IAC34MODE DBCR1_IAC34MX /* IAC 3-4 Mode Bits */
+
/* Bit definitions related to the DBCR2. */
+#define DBCR2_DAC1US 0xC0000000 /* Data Addr Cmp 1 Sup/User */
+#define DBCR2_DAC1ER 0x30000000 /* Data Addr Cmp 1 Eff/Real */
+#define DBCR2_DAC2US 0x00000000 /* Data Addr Cmp 2 Sup/User */
+#define DBCR2_DAC2ER 0x00000000 /* Data Addr Cmp 2 Eff/Real */
#define DBCR2_DAC12M 0x00800000 /* DAC 1-2 range enable */
+#define DBCR2_DAC12MM 0x00400000 /* DAC 1-2 Mask mode*/
#define DBCR2_DAC12MX 0x00C00000 /* DAC 1-2 range eXclusive */
+#define DBCR2_DAC12MODE 0x00C00000 /* DAC 1-2 Mode Bits */
#define DBCR2_DAC12A 0x00200000 /* DAC 1-2 Asynchronous */
-#endif
+#define DBCR2_DVC1M 0x000C0000 /* Data Value Comp 1 Mode */
+#define DBCR2_DVC1M_SHIFT 18 /* # of bits to shift DBCR2_DVC1M */
+#define DBCR2_DVC2M 0x00030000 /* Data Value Comp 2 Mode */
+#define DBCR2_DVC2M_SHIFT 16 /* # of bits to shift DBCR2_DVC2M */
+#define DBCR2_DVC1BE 0x00000F00 /* Data Value Comp 1 Byte */
+#define DBCR2_DVC1BE_SHIFT 8 /* # of bits to shift DBCR2_DVC1BE */
+#define DBCR2_DVC2BE 0x0000000F /* Data Value Comp 2 Byte */
+#define DBCR2_DVC2BE_SHIFT 0 /* # of bits to shift DBCR2_DVC2BE */
+
+/*
+ * Are there any active Debug Events represented in the
+ * Debug Control Registers?
+ */
+#define DBCR0_ACTIVE_EVENTS (DBCR0_ICMP | DBCR0_IAC1 | DBCR0_IAC2 | \
+ DBCR0_IAC3 | DBCR0_IAC4 | DBCR0_DAC1R | \
+ DBCR0_DAC1W | DBCR0_DAC2R | DBCR0_DAC2W)
+#define DBCR1_ACTIVE_EVENTS 0
+
+#define DBCR_ACTIVE_EVENTS(dbcr0, dbcr1) (((dbcr0) & DBCR0_ACTIVE_EVENTS) || \
+ ((dbcr1) & DBCR1_ACTIVE_EVENTS))
+#endif /* #elif defined(CONFIG_BOOKE) */
/* Bit definitions related to the TCR. */
#define TCR_WP(x) (((x)&0x3)<<30) /* WDT Period */
--
Dave Kleikamp
IBM Linux Technology Center
^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [RFC:PATCH 01/03] powerpc: Extended ptrace interface
2010-01-18 21:57 ` [RFC:PATCH 01/03] powerpc: Extended " Dave Kleikamp
@ 2010-01-21 2:47 ` Michael Neuling
2010-02-01 5:08 ` Benjamin Herrenschmidt
0 siblings, 1 reply; 9+ messages in thread
From: Michael Neuling @ 2010-01-21 2:47 UTC (permalink / raw)
To: Dave Kleikamp
Cc: linuxppc-dev list, Sergio Durigan Junior, Torez Smith,
Thiago Jung Bauermann, David Gibson
> powerpc: Extended ptrace interface
>
> From: Torez Smith <lnxtorez@linux.vnet.ibm.com>
>
> Add a new extended ptrace interface so that user-space has a single
> interface for powerpc, without having to know the specific layout
> of the debug registers.
>
> Implement:
> PPC_PTRACE_GETHWDEBUGINFO
> PPC_PTRACE_SETHWDEBUG
> PPC_PTRACE_DELHWDEBUG
>
> Signed-off-by: Torez Smith <lnxtorez@linux.vnet.ibm.com>
> Signed-off-by: Dave Kleikamp <shaggy@linux.vnet.ibm.com>
> Acked-by: David Gibson <dwg@au1.ibm.com>
> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> Cc: Josh Boyer <jwboyer@linux.vnet.ibm.com>
> Cc: Kumar Gala <galak@kernel.crashing.org>
> Cc: Sergio Durigan Junior <sergiodj@br.ibm.com>
> Cc: Thiago Jung Bauermann <bauerman@br.ibm.com>
> Cc: linuxppc-dev list <Linuxppc-dev@ozlabs.org>
> ---
>
> Documentation/powerpc/ptrace.txt | 134 +++++++++++++++++++++++++++++++++++
++
> arch/powerpc/include/asm/ptrace.h | 77 +++++++++++++++++++++
> arch/powerpc/kernel/ptrace.c | 90 +++++++++++++++++++++++++
> 3 files changed, 301 insertions(+), 0 deletions(-)
> create mode 100644 Documentation/powerpc/ptrace.txt
>
>
> diff --git a/Documentation/powerpc/ptrace.txt b/Documentation/powerpc/ptrace.
txt
> new file mode 100644
> index 0000000..f4a5499
> --- /dev/null
> +++ b/Documentation/powerpc/ptrace.txt
> @@ -0,0 +1,134 @@
> +GDB intends to support the following hardware debug features of BookE
> +processors:
> +
> +4 hardware breakpoints (IAC)
> +2 hardware watchpoints (read, write and read-write) (DAC)
> +2 value conditions for the hardware watchpoints (DVC)
> +
> +For that, we need to extend ptrace so that GDB can query and set these
> +resources. Since we're extending, we're trying to create an interface
> +that's extendable and that covers both BookE and server processors, so
> +that GDB doesn't need to special-case each of them. We added the
> +following 3 new ptrace requests.
> +
> +1. PTRACE_PPC_GETHWDEBUGINFO
> +
> +Query for GDB to discover the hardware debug features. The main info to
> +be returned here is the minimum alignment for the hardware watchpoints.
> +BookE processors don't have restrictions here, but server processors have
> +an 8-byte alignment restriction for hardware watchpoints. We'd like to avoid
> +adding special cases to GDB based on what it sees in AUXV.
> +
> +Since we're at it, we added other useful info that the kernel can return to
> +GDB: this query will return the number of hardware breakpoints, hardware
> +watchpoints and whether it supports a range of addresses and a condition.
> +The query will fill the following structure provided by the requesting proce
ss:
> +
> +struct ppc_debug_info {
> + unit32_t version;
> + unit32_t num_instruction_bps;
> + unit32_t num_data_bps;
> + unit32_t num_condition_regs;
> + unit32_t data_bp_alignment;
> + unit32_t sizeof_condition; /* size of the DVC register */
> + uint64_t features; /* bitmask of the individual flags */
> +};
> +
> +features will have bits indicating whether there is support for:
> +
> +#define PPC_DEBUG_FEATURE_INSN_BP_RANGE 0x1
> +#define PPC_DEBUG_FEATURE_INSN_BP_MASK 0x2
> +#define PPC_DEBUG_FEATURE_DATA_BP_RANGE 0x4
> +#define PPC_DEBUG_FEATURE_DATA_BP_MASK 0x8
> +
> +2. PTRACE_SETHWDEBUG
> +
> +Sets a hardware breakpoint or watchpoint, according to the provided structur
e:
> +
> +struct ppc_hw_breakpoint {
> + uint32_t version;
> +#define PPC_BREAKPOINT_TRIGGER_EXECUTE 0x1
> +#define PPC_BREAKPOINT_TRIGGER_READ 0x2
> +#define PPC_BREAKPOINT_TRIGGER_WRITE 0x4
> + uint32_t trigger_type; /* only some combinations allowed */
> +#define PPC_BREAKPOINT_MODE_EXACT 0x0
> +#define PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE 0x1
> +#define PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE 0x2
> +#define PPC_BREAKPOINT_MODE_MASK 0x3
> + uint32_t addr_mode; /* address match mode */
> +
> +#define PPC_BREAKPOINT_CONDITION_MODE 0x3
> +#define PPC_BREAKPOINT_CONDITION_NONE 0x0
> +#define PPC_BREAKPOINT_CONDITION_AND 0x1
> +#define PPC_BREAKPOINT_CONDITION_EXACT 0x1 /* different name for the same
thing as above */
> +#define PPC_BREAKPOINT_CONDITION_OR 0x2
> +#define PPC_BREAKPOINT_CONDITION_AND_OR 0x3
> +#define PPC_BREAKPOINT_CONDITION_BE_ALL 0x00ff0000 /* byte enable bits */
> +#define PPC_BREAKPOINT_CONDITION_BE(n) (1<<((n)+16))
> + uint32_t condition_mode; /* break/watchpoint condition flags */
> +
> + uint64_t addr;
> + uint64_t addr2;
> + uint64_t condition_value;
> +};
> +
> +A request specifies one event, not necessarily just one register to be set.
> +For instance, if the request is for a watchpoint with a condition, both the
> +DAC and DVC registers will be set in the same request.
> +
> +With this GDB can ask for all kinds of hardware breakpoints and watchpoints
> +that the BookE supports. COMEFROM breakpoints available in server processors
> +are not contemplated, but that is out of the scope of this work.
> +
> +ptrace will return an integer (handle) uniquely identifying the breakpoint o
r
> +watchpoint just created. This integer will be used in the PTRACE_DELHWDEBUG
> +request to ask for its removal. Return -ENOSPC if the requested breakpoint
> +can't be allocated on the registers.
> +
> +Some examples of using the structure to:
> +
> +- set a breakpoint in the first breakpoint register
> +
> + p.version = PPC_DEBUG_CURRENT_VERSION;
> + p.trigger_type = PPC_BREAKPOINT_TRIGGER_EXECUTE;
> + p.addr_mode = PPC_BREAKPOINT_MODE_EXACT;
> + p.condition_mode = PPC_BREAKPOINT_CONDITION_NONE;
> + p.addr = (uint64_t) address;
> + p.addr2 = 0;
> + p.condition_value = 0;
> +
> +- set a watchpoint which triggers on reads in the second watchpoint register
> +
> + p.version = PPC_DEBUG_CURRENT_VERSION;
> + p.trigger_type = PPC_BREAKPOINT_TRIGGER_READ;
> + p.addr_mode = PPC_BREAKPOINT_MODE_EXACT;
> + p.condition_mode = PPC_BREAKPOINT_CONDITION_NONE;
> + p.addr = (uint64_t) address;
> + p.addr2 = 0;
> + p.condition_value = 0;
> +
> +- set a watchpoint which triggers only with a specific value
> +
> + p.version = PPC_DEBUG_CURRENT_VERSION;
> + p.trigger_type = PPC_BREAKPOINT_TRIGGER_READ;
> + p.addr_mode = PPC_BREAKPOINT_MODE_EXACT;
> + p.condition_mode = PPC_BREAKPOINT_CONDITION_AND | PPC_BREAKPOINT_CONDITIO
N_BE_ALL;
> + p.addr = (uint64_t) address;
> + p.addr2 = 0;
> + p.condition_value = (uint64_t) condition;
> +
> +- set a ranged hardware breakpoint
> +
> + p.version = PPC_DEBUG_CURRENT_VERSION;
> + p.trigger_type = PPC_BREAKPOINT_TRIGGER_EXECUTE;
> + p.addr_mode = PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE;
> + p.condition_mode = PPC_BREAKPOINT_CONDITION_NONE;
> + p.addr = (uint64_t) begin_range;
> + p.addr2 = (uint64_t) end_range;
> + p.condition_value = 0;
> +
> +3. PTRACE_DELHWDEBUG
> +
> +Takes an integer which identifies an existing breakpoint or watchpoint
> +(i.e., the value returned from PTRACE_SETHWDEBUG), and deletes the
> +corresponding breakpoint or watchpoint..
> diff --git a/arch/powerpc/include/asm/ptrace.h b/arch/powerpc/include/asm/ptr
ace.h
> index cbd759e..b451081 100644
> --- a/arch/powerpc/include/asm/ptrace.h
> +++ b/arch/powerpc/include/asm/ptrace.h
> @@ -24,6 +24,12 @@
> * 2 of the License, or (at your option) any later version.
> */
>
> +#ifdef __KERNEL__
> +#include <linux/types.h>
> +#else
> +#include <stdint.h>
> +#endif
> +
> #ifndef __ASSEMBLY__
>
> struct pt_regs {
> @@ -294,4 +300,75 @@ extern void user_disable_single_step(struct task_struct
*);
>
> #define PTRACE_SINGLEBLOCK 0x100 /* resume execution until next branch *
/
>
> +#define PPC_PTRACE_GETHWDBGINFO 0x89
> +#define PPC_PTRACE_SETHWDEBUG 0x88
> +#define PPC_PTRACE_DELHWDEBUG 0x87
> +
> +#ifndef __ASSEMBLY__
> +
> +struct ppc_debug_info {
> + uint32_t version; /* Only version 1 exists to date */
> + uint32_t num_instruction_bps;
> + uint32_t num_data_bps;
> + uint32_t num_condition_regs;
> + uint32_t data_bp_alignment;
> + uint32_t sizeof_condition; /* size of the DVC register */
> + uint64_t features;
> +};
> +
> +#endif /* __ASSEMBLY__ */
> +
> +/*
> + * features will have bits indication whether there is support for:
> + */
> +#define PPC_DEBUG_FEATURE_INSN_BP_RANGE 0x0000000000000001
> +#define PPC_DEBUG_FEATURE_INSN_BP_MASK 0x0000000000000002
> +#define PPC_DEBUG_FEATURE_DATA_BP_RANGE 0x0000000000000004
> +#define PPC_DEBUG_FEATURE_DATA_BP_MASK 0x0000000000000008
> +
> +#ifndef __ASSEMBLY__
> +
> +struct ppc_hw_breakpoint {
> + uint32_t version; /* currently, version must be 1 */
> + uint32_t trigger_type; /* only some combinations allowed */
> + uint32_t addr_mode; /* address match mode */
> + uint32_t condition_mode; /* break/watchpoint condition flags */
> + uint64_t addr; /* break/watchpoint address */
> + uint64_t addr2; /* range end or mask */
> + uint64_t condition_value; /* contents of the DVC register */
> +};
> +
> +#endif /* __ASSEMBLY__ */
> +
> +/*
> + * Trigger Type
> + */
> +#define PPC_BREAKPOINT_TRIGGER_EXECUTE 0x00000001
> +#define PPC_BREAKPOINT_TRIGGER_READ 0x00000002
> +#define PPC_BREAKPOINT_TRIGGER_WRITE 0x00000004
> +#define PPC_BREAKPOINT_TRIGGER_RW \
> + (PPC_BREAKPOINT_TRIGGER_READ | PPC_BREAKPOINT_TRIGGER_WRITE)
> +
> +/*
> + * Address Mode
> + */
> +#define PPC_BREAKPOINT_MODE_EXACT 0x00000000
> +#define PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE 0x00000001
> +#define PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE 0x00000002
> +#define PPC_BREAKPOINT_MODE_MASK 0x00000003
> +
> +/*
> + * Condition Mode
> + */
> +#define PPC_BREAKPOINT_CONDITION_MODE 0x00000003
> +#define PPC_BREAKPOINT_CONDITION_NONE 0x00000000
> +#define PPC_BREAKPOINT_CONDITION_AND 0x00000001
> +#define PPC_BREAKPOINT_CONDITION_EXACT PPC_BREAKPOINT_CONDITION_AND
> +#define PPC_BREAKPOINT_CONDITION_OR 0x00000002
> +#define PPC_BREAKPOINT_CONDITION_AND_OR 0x00000003
> +#define PPC_BREAKPOINT_CONDITION_BE_ALL 0x00ff0000
> +#define PPC_BREAKPOINT_CONDITION_BE_SHIFT 16
> +#define PPC_BREAKPOINT_CONDITION_BE(n) \
> + (1<<((n)+PPC_BREAKPOINT_CONDITION_BE_SHIFT))
> +
> #endif /* _ASM_POWERPC_PTRACE_H */
> diff --git a/arch/powerpc/kernel/ptrace.c b/arch/powerpc/kernel/ptrace.c
> index ef14988..33ab496 100644
> --- a/arch/powerpc/kernel/ptrace.c
> +++ b/arch/powerpc/kernel/ptrace.c
> @@ -839,6 +839,52 @@ void ptrace_disable(struct task_struct *child)
> user_disable_single_step(child);
> }
>
> +static long ppc_set_hwdebug(struct task_struct *child,
> + struct ppc_hw_breakpoint *bp_info)
> +{
> + /*
> + * We currently support one data breakpoint
> + */
> + if (((bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_RW) == 0) ||
> + ((bp_info->trigger_type & ~PPC_BREAKPOINT_TRIGGER_RW) != 0) ||
> + (bp_info->trigger_type != PPC_BREAKPOINT_TRIGGER_WRITE) ||
> + (bp_info->addr_mode != PPC_BREAKPOINT_MODE_EXACT) ||
> + (bp_info->condition_mode != PPC_BREAKPOINT_CONDITION_NONE))
> + return -EINVAL;
> +
> + if (child->thread.dabr)
> + return -ENOSPC;
> +
> + if ((unsigned long)bp_info->addr >= TASK_SIZE)
> + return -EIO;
> +
> + child->thread.dabr = (unsigned long)bp_info->addr;
> +#ifdef CONFIG_BOOKE
Do we want to add these CONFIG_BOOKE into a ppc_md call, so different
CPU typs can have different setups? I could see other CPUs might need
to do different stuff here and we end up in #ifdef chaos
> + child->thread.dbcr0 = DBCR0_IDM;
> + if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_READ)
> + child->thread.dbcr0 |= DBSR_DAC1R;
> + if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_WRITE)
> + child->thread.dbcr0 |= DBSR_DAC1W;
> + child->thread.regs->msr |= MSR_DE;
> +#endif
> + return 1;
> +}
> +
> +static long ppc_del_hwdebug(struct task_struct *child, long addr, long data)
> +{
addr is not used.
> + if (data != 1)
> + return -EINVAL;
.. other than this test, data is not being used.
Could probably just stick this function inline in the case statement
below like the other cases.
> + if (child->thread.dabr == 0)
> + return -ENOENT;
> +
> + child->thread.dabr = 0;
> +#ifdef CONFIG_BOOKE
> + child->thread.dbcr0 &= ~(DBSR_DAC1R | DBSR_DAC1W | DBCR0_IDM);
> + child->thread.regs->msr &= ~MSR_DE;
> +#endif
> + return 0;
> +}
> +
> /*
> * Here are the old "legacy" powerpc specific getregs/setregs ptrace calls,
> * we mark them as obsolete now, they will be removed in a future version
> @@ -932,6 +978,50 @@ long arch_ptrace(struct task_struct *child, long request
, long addr, long data)
> break;
> }
>
> + case PPC_PTRACE_GETHWDBGINFO: {
> + struct ppc_debug_info dbginfo;
> +
> + dbginfo.version = 1;
> + dbginfo.num_instruction_bps = 0;
> + dbginfo.num_data_bps = 1;
> + dbginfo.num_condition_regs = 0;
> +#ifdef CONFIG_PPC64
> + dbginfo.data_bp_alignment = 8;
> +#else
> + dbginfo.data_bp_alignment = 4;
> +#endif
> + dbginfo.sizeof_condition = 0;
> + dbginfo.features = 0;
> +
> + if (!access_ok(VERIFY_WRITE, data,
> + sizeof(struct ppc_debug_info)))
> + return -EFAULT;
> + ret = __copy_to_user((struct ppc_debug_info __user *)data,
> + &dbginfo, sizeof(struct ppc_debug_info)) ?
> + -EFAULT : 0;
> + break;
> + }
> +
> + case PPC_PTRACE_SETHWDEBUG: {
> + struct ppc_hw_breakpoint bp_info;
> +
> + if (!access_ok(VERIFY_READ, data,
> + sizeof(struct ppc_hw_breakpoint)))
> + return -EFAULT;
> + ret = __copy_from_user(&bp_info,
> + (struct ppc_hw_breakpoint __user *)data,
> + sizeof(struct ppc_hw_breakpoint)) ?
> + -EFAULT : 0;
> + if (!ret)
> + ret = ppc_set_hwdebug(child, &bp_info);
> + break;
> + }
> +
> + case PPC_PTRACE_DELHWDEBUG: {
> + ret = ppc_del_hwdebug(child, addr, data);
> + break;
> + }
> +
> case PTRACE_GET_DEBUGREG: {
> ret = -EINVAL;
> /* We only support one DABR and no IABRS at the moment */
>
> --
> Dave Kleikamp
> IBM Linux Technology Center
> _______________________________________________
> Linuxppc-dev mailing list
> Linuxppc-dev@lists.ozlabs.org
> https://lists.ozlabs.org/listinfo/linuxppc-dev
>
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [RFC:PATCH 01/03] powerpc: Extended ptrace interface
2010-01-21 2:47 ` Michael Neuling
@ 2010-02-01 5:08 ` Benjamin Herrenschmidt
0 siblings, 0 replies; 9+ messages in thread
From: Benjamin Herrenschmidt @ 2010-02-01 5:08 UTC (permalink / raw)
To: Michael Neuling
Cc: Thiago Jung Bauermann, Dave Kleikamp, David Gibson,
linuxppc-dev list, Torez Smith, Sergio Durigan Junior
On Thu, 2010-01-21 at 15:47 +1300, Michael Neuling wrote:
> > powerpc: Extended ptrace interface
> > +static long ppc_set_hwdebug(struct task_struct *child,
> > + struct ppc_hw_breakpoint *bp_info)
> > +{
> > + /*
> > + * We currently support one data breakpoint
> > + */
> > + if (((bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_RW) == 0) ||
> > + ((bp_info->trigger_type & ~PPC_BREAKPOINT_TRIGGER_RW) != 0) ||
> > + (bp_info->trigger_type != PPC_BREAKPOINT_TRIGGER_WRITE) ||
> > + (bp_info->addr_mode != PPC_BREAKPOINT_MODE_EXACT) ||
> > + (bp_info->condition_mode != PPC_BREAKPOINT_CONDITION_NONE))
> > + return -EINVAL;
> > +
> > + if (child->thread.dabr)
> > + return -ENOSPC;
> > +
> > + if ((unsigned long)bp_info->addr >= TASK_SIZE)
> > + return -EIO;
> > +
> > + child->thread.dabr = (unsigned long)bp_info->addr;
> > +#ifdef CONFIG_BOOKE
>
> Do we want to add these CONFIG_BOOKE into a ppc_md call, so different
> CPU typs can have different setups? I could see other CPUs might need
> to do different stuff here and we end up in #ifdef chaos
Actually, I don't think we need that level of indirection just now. If
there's ever a need for more ifdef's then ok, but the BookE debug
facility is somewhat architected so I wouldn't expect that much new
stuff.
Cheers,
Ben.
^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2010-02-01 5:08 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2010-01-18 21:57 [RFC:PATCH 00/03] powerpc: Expose BookE debug registers through extended ptrace interface Dave Kleikamp
2010-01-18 21:57 ` [RFC:PATCH 01/03] powerpc: Extended " Dave Kleikamp
2010-01-21 2:47 ` Michael Neuling
2010-02-01 5:08 ` Benjamin Herrenschmidt
2010-01-18 21:57 ` [RFC:PATCH 03/03] powerpc: Add support for BookE Debug Reg. traps, exceptions and ptrace Dave Kleikamp
2010-01-18 21:59 ` [RFC:PATCH 02/03] powerpc: Add definitions for Debug Registers on BookE Platforms Dave Kleikamp
-- strict thread matches above, loose matches on Subject: below --
2009-12-10 15:57 [RFC:PATCH 00/03] powerpc: Expose BookE debug registers through extended ptrace interface Dave Kleikamp
2009-12-10 15:57 ` [RFC:PATCH 01/03] powerpc: Extended " Dave Kleikamp
2009-12-11 0:44 ` David Gibson
2009-12-11 2:51 ` Kumar Gala
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