From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx0a-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3sMnKC3Hl3zDrgX for ; Mon, 29 Aug 2016 07:02:07 +1000 (AEST) Received: from pps.filterd (m0098420.ppops.net [127.0.0.1]) by mx0b-001b2d01.pphosted.com (8.16.0.11/8.16.0.11) with SMTP id u7SKx1CK110241 for ; Sun, 28 Aug 2016 17:02:05 -0400 Received: from e28smtp08.in.ibm.com (e28smtp08.in.ibm.com [125.16.236.8]) by mx0b-001b2d01.pphosted.com with ESMTP id 253r50f121-1 (version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT) for ; Sun, 28 Aug 2016 17:02:04 -0400 Received: from localhost by e28smtp08.in.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Mon, 29 Aug 2016 02:32:01 +0530 Received: from d28relay01.in.ibm.com (d28relay01.in.ibm.com [9.184.220.58]) by d28dlp03.in.ibm.com (Postfix) with ESMTP id 0A93E1258061 for ; Mon, 29 Aug 2016 02:32:01 +0530 (IST) Received: from d28av01.in.ibm.com (d28av01.in.ibm.com [9.184.220.63]) by d28relay01.in.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id u7SL1x9b18546854 for ; Mon, 29 Aug 2016 02:31:59 +0530 Received: from d28av01.in.ibm.com (localhost [127.0.0.1]) by d28av01.in.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id u7SL1ru6006138 for ; Mon, 29 Aug 2016 02:31:59 +0530 From: Madhavan Srinivasan To: linux-kernel@vger.kernel.org, linuxppc-dev@lists.ozlabs.org Cc: Madhavan Srinivasan , Thomas Gleixner , Ingo Molnar , Peter Zijlstra , Jiri Olsa , Arnaldo Carvalho de Melo , Stephane Eranian , Russell King , Catalin Marinas , Will Deacon , Benjamin Herrenschmidt , Michael Ellerman , Sukadev Bhattiprolu Subject: [PATCH 07/13] powerpc/perf: Add support for perf_arch_regs for Power7 processor Date: Mon, 29 Aug 2016 02:30:52 +0530 In-Reply-To: <1472418058-28659-1-git-send-email-maddy@linux.vnet.ibm.com> References: <1472418058-28659-1-git-send-email-maddy@linux.vnet.ibm.com> Message-Id: <1472418058-28659-8-git-send-email-maddy@linux.vnet.ibm.com> List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Add code to define support functions and registers mask for Power7 processor. Cc: Thomas Gleixner Cc: Ingo Molnar Cc: Peter Zijlstra Cc: Jiri Olsa Cc: Arnaldo Carvalho de Melo Cc: Stephane Eranian Cc: Russell King Cc: Catalin Marinas Cc: Will Deacon Cc: Benjamin Herrenschmidt Cc: Michael Ellerman Cc: Sukadev Bhattiprolu Signed-off-by: Madhavan Srinivasan --- arch/powerpc/perf/power7-pmu.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/powerpc/perf/power7-pmu.c b/arch/powerpc/perf/power7-pmu.c index a383c23a9070..1eac466d4881 100644 --- a/arch/powerpc/perf/power7-pmu.c +++ b/arch/powerpc/perf/power7-pmu.c @@ -13,6 +13,7 @@ #include #include #include +#include /* * Bits in event code for POWER7 @@ -427,6 +428,31 @@ static const struct attribute_group *power7_pmu_attr_groups[] = { NULL, }; +#define POWER7_ARCH_REGS_MASK (PERF_ARCH_REG_PVR |\ + PERF_ARCH_REG_PMC1 | PERF_ARCH_REG_PMC2 |\ + PERF_ARCH_REG_PMC3 | PERF_ARCH_REG_PMC4 |\ + PERF_ARCH_REG_PMC5 | PERF_ARCH_REG_PMC6 |\ + PERF_ARCH_REG_MMCR0 | PERF_ARCH_REG_MMCR1 |\ + PERF_ARCH_REG_SIER | PERF_ARCH_REG_SIAR |\ + PERF_ARCH_REG_SDAR | PERF_ARCH_REG_MMCRA) + +static void power7_get_arch_regs(struct perf_arch_regs *regs) +{ + regs->regs[PERF_ARCH_REG_POWERPC_PVR] = mfspr(SPRN_PVR); + regs->regs[PERF_ARCH_REG_POWERPC_PMC1] = mfspr(SPRN_PMC1); + regs->regs[PERF_ARCH_REG_POWERPC_PMC2] = mfspr(SPRN_PMC2); + regs->regs[PERF_ARCH_REG_POWERPC_PMC3] = mfspr(SPRN_PMC3); + regs->regs[PERF_ARCH_REG_POWERPC_PMC4] = mfspr(SPRN_PMC4); + regs->regs[PERF_ARCH_REG_POWERPC_PMC5] = mfspr(SPRN_PMC5); + regs->regs[PERF_ARCH_REG_POWERPC_PMC6] = mfspr(SPRN_PMC6); + regs->regs[PERF_ARCH_REG_POWERPC_MMCR0] = mfspr(SPRN_MMCR0); + regs->regs[PERF_ARCH_REG_POWERPC_MMCR1] = mfspr(SPRN_MMCR1); + regs->regs[PERF_ARCH_REG_POWERPC_SIER] = mfspr(SPRN_SIER); + regs->regs[PERF_ARCH_REG_POWERPC_SIAR] = mfspr(SPRN_SIAR); + regs->regs[PERF_ARCH_REG_POWERPC_SDAR] = mfspr(SPRN_SDAR); + regs->regs[PERF_ARCH_REG_POWERPC_MMCRA] = mfspr(SPRN_MMCRA); +} + static struct power_pmu power7_pmu = { .name = "POWER7", .n_counter = 6, @@ -442,6 +468,8 @@ static struct power_pmu power7_pmu = { .n_generic = ARRAY_SIZE(power7_generic_events), .generic_events = power7_generic_events, .cache_events = &power7_cache_events, + .ar_mask = POWER7_ARCH_REGS_MASK, + .get_arch_regs = power7_get_arch_regs, }; static int __init init_power7_pmu(void) -- 2.7.4