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Subject: Re: [bug report] [POWERPC] 4xx: Add 405GPr and 405EP support in
 boot wrapper
From: Benjamin Herrenschmidt <benh@au1.ibm.com>
Reply-To: benh@au1.ibm.com
To: Dan Carpenter <dan.carpenter@oracle.com>
Cc: matthias.fuchs@esd-electronics.com, linuxppc-dev@lists.ozlabs.org
Date: Wed, 26 Oct 2016 15:50:39 -0500
In-Reply-To: <20161026190702.GS4418@mwanda>
References: <20161026130311.GA3080@elgon.mountain>
 <1477508243.2828.70.camel@au1.ibm.com> <20161026190702.GS4418@mwanda>
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On Wed, 2016-10-26 at 22:07 +0300, Dan Carpenter wrote:
> On Wed, Oct 26, 2016 at 01:57:23PM -0500, Benjamin Herrenschmidt
> wrote:
> > 
> > On Wed, 2016-10-26 at 16:03 +0300, Dan Carpenter wrote:
> > > 
> > >    565          cbdv = ((pllmr & 0x00060000) >> 17) + 1; /*
> > > CPU:PLB */
> > >    566          opdv = ((pllmr & 0x00018000) >> 15) + 1; /*
> > > PLB:OPB */
> > >    567          ppdv = ((pllmr & 0x00001800) >> 13) + 1; /*
> > > PLB:PCI */
> > >                                  ^^^^^^^^^^^^^^^^^
> > > This is zero.  It looks like 0x00000600 was probably intended?
> > 
> > I just checked the spec and for the 405gp and it's 0x6000 (bits 17
> > and
> > 18 in IBM ordering)
> > 
> 
> I'm on the road and there is no way I'm going to remember to do this
> when I get back...  Could you send the patch?

I'll try to remember when I'm out of meeting frenzy ;-)

Cheers,
Ben.