From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from leibniz.telenet-ops.be (leibniz.telenet-ops.be [IPv6:2a02:1800:110:4::f00:d]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3t6scq4X8zzDvJB for ; Mon, 31 Oct 2016 22:31:07 +1100 (AEDT) Received: from andre.telenet-ops.be (andre.telenet-ops.be [IPv6:2a02:1800:120:4::f00:15]) by leibniz.telenet-ops.be (Postfix) with ESMTPS id 3t6scj48PHzMqvZ6 for ; Mon, 31 Oct 2016 12:31:01 +0100 (CET) From: Geert Uytterhoeven To: Arnd Bergmann , Greg Kroah-Hartman , Yangbo Lu , Simon Horman , Magnus Damm , Rob Herring , Mark Rutland Cc: Dirk Behme , linux-renesas-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linuxppc-dev@lists.ozlabs.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH v2 5/7] ARM: shmobile: Document DT bindings for CCCR and PRR Date: Mon, 31 Oct 2016 12:30:53 +0100 Message-Id: <1477913455-5314-6-git-send-email-geert+renesas@glider.be> In-Reply-To: <1477913455-5314-1-git-send-email-geert+renesas@glider.be> References: <1477913455-5314-1-git-send-email-geert+renesas@glider.be> List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Add device tree binding documentation for the Common Chip Code Register and Product Register, which provide SoC product and revision information. Signed-off-by: Geert Uytterhoeven --- v2: - New. --- Documentation/devicetree/bindings/arm/shmobile.txt | 26 ++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt b/Documentation/devicetree/bindings/arm/shmobile.txt index 15669642b5324412..bff1b596b235c535 100644 --- a/Documentation/devicetree/bindings/arm/shmobile.txt +++ b/Documentation/devicetree/bindings/arm/shmobile.txt @@ -79,3 +79,29 @@ Boards: compatible = "renesas,sk-rzg1m", "renesas,r8a7743" - Wheat compatible = "renesas,wheat", "renesas,r8a7792" + + +Most Renesas ARM SoCs have one or two registers (Common Chip Code +Register and/or Product Register) that allow to retrieve SoC product and +revision information. If present, device nodes for these devices should +be added. + +Required properties: + - compatible: Must be one of: + - "renesas,cccr" for the Common Chip Code Register, + - "renesas,prr" for the Product Register. + - reg: Base address and length of the register block. + + +Examples +-------- + + cccr: chipid@e600101c { + compatible = "renesas,cccr"; + reg = <0xe600101c 4>; + }; + + prr: chipid@ff000044 { + compatible = "renesas,prr"; + reg = <0 0xff000044 0 4>; + }; -- 1.9.1