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Message-ID: <1481642851.17253.72.camel@kernel.crashing.org>
Subject: Re: [powerpc/nmi: RFC 2/2] Keep interrupts enabled even on soft
 disable
From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
To: Balbir Singh <bsingharora@gmail.com>, Nicholas Piggin <npiggin@gmail.com>
Cc: linuxppc-dev@ozlabs.org, Michael Ellerman <mpe@ellerman.id.au>, Paul
 Mackerras <paulus@samba.org>
Date: Tue, 13 Dec 2016 09:27:31 -0600
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On Tue, 2016-12-13 at 16:36 +1100, Balbir Singh wrote:
> Yep, although the code works for PPC_XICS only which is good for now.
> When we do XIVE, we can add more bits

We may want to do XIVE differently, dunno. On XIVE we can just poke the
processor priority with a single MMIO store, so we don't actually need
to "fetch" the interrupt and we can continue doing separate priorities.

Note that raising the priority would work on XICS in *theory* as well
but HW bugs get in the way if we do that.

We also need to make sure you either adjust MPIC and all other PICs
potentially used on ppc64 to do this "only one priority" thing or you
disable that new mechanism on all those PICs.

That's why I mentioned opt-in. Maybe make it conditional on a global
boolean that gets enabled by the PIC itself, or make it an enum

enum lazy_irq_masking_mode {
	lazy_irq_mask_ee,	/* Use CPU EE bit (default) */
	lazy_irq_mask_fetch,	/* Fetch the interrupt and stash it away */
	lazy_irq_mask_prio	/* Change processor priority */
};

For the latter we'd need a ppc_md. hook to do the priority change
which xive (and potentially others like MPIC) could use.

Cheers,
Ben.