* [PATCH 2/5] powerpc/mm: Express everything based on Radix page table defines
2017-02-21 8:19 [PATCH 1/5] powerpc/mm: Conditional defines of pte bits are messy Aneesh Kumar K.V
@ 2017-02-21 8:19 ` Aneesh Kumar K.V
2017-02-21 8:19 ` [PATCH 3/5] powerpc/mm: Lower the max real address to 51 bits Aneesh Kumar K.V
` (2 subsequent siblings)
3 siblings, 0 replies; 5+ messages in thread
From: Aneesh Kumar K.V @ 2017-02-21 8:19 UTC (permalink / raw)
To: benh, paulus, mpe; +Cc: linuxppc-dev, Aneesh Kumar K.V
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
---
arch/powerpc/include/asm/book3s/64/hash-64k.h | 4 ++--
arch/powerpc/include/asm/book3s/64/pgtable.h | 2 ++
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/include/asm/book3s/64/hash-64k.h b/arch/powerpc/include/asm/book3s/64/hash-64k.h
index b39f0b86405e..7be54f9590a3 100644
--- a/arch/powerpc/include/asm/book3s/64/hash-64k.h
+++ b/arch/powerpc/include/asm/book3s/64/hash-64k.h
@@ -10,8 +10,8 @@
* 64k aligned address free up few of the lower bits of RPN for us
* We steal that here. For more deatils look at pte_pfn/pfn_pte()
*/
-#define H_PAGE_COMBO 0x00001000 /* this is a combo 4k page */
-#define H_PAGE_4K_PFN 0x00002000 /* PFN is for a single 4k page */
+#define H_PAGE_COMBO _RPAGE_RPN0 /* this is a combo 4k page */
+#define H_PAGE_4K_PFN _RPAGE_RPN1 /* PFN is for a single 4k page */
/*
* We need to differentiate between explicit huge page and THP huge
* page, since THP huge page also need to track real subpage details
diff --git a/arch/powerpc/include/asm/book3s/64/pgtable.h b/arch/powerpc/include/asm/book3s/64/pgtable.h
index 8ae9e0be3a6f..dec136742cd7 100644
--- a/arch/powerpc/include/asm/book3s/64/pgtable.h
+++ b/arch/powerpc/include/asm/book3s/64/pgtable.h
@@ -30,6 +30,8 @@
#define _RPAGE_RSV2 0x0800000000000000UL
#define _RPAGE_RSV3 0x0400000000000000UL
#define _RPAGE_RSV4 0x0200000000000000UL
+#define _RPAGE_RPN0 0x01000
+#define _RPAGE_RPN1 0x02000
#define _PAGE_SOFT_DIRTY _RPAGE_SW3 /* software: software dirty tracking */
#define _PAGE_SPECIAL _RPAGE_SW2 /* software: special page */
--
2.7.4
^ permalink raw reply related [flat|nested] 5+ messages in thread* [PATCH 3/5] powerpc/mm: Lower the max real address to 51 bits
2017-02-21 8:19 [PATCH 1/5] powerpc/mm: Conditional defines of pte bits are messy Aneesh Kumar K.V
2017-02-21 8:19 ` [PATCH 2/5] powerpc/mm: Express everything based on Radix page table defines Aneesh Kumar K.V
@ 2017-02-21 8:19 ` Aneesh Kumar K.V
2017-02-21 8:19 ` [PATCH 4/5] powerpc/mm/radix: Make max pfn bits a variable Aneesh Kumar K.V
2017-02-21 8:19 ` [PATCH 5/5] powerpc/mm: Move hash specific pte bits to be top bits of RPN Aneesh Kumar K.V
3 siblings, 0 replies; 5+ messages in thread
From: Aneesh Kumar K.V @ 2017-02-21 8:19 UTC (permalink / raw)
To: benh, paulus, mpe; +Cc: linuxppc-dev, Aneesh Kumar K.V
Max value supported by hardware is 51 bits address. Radix page table define
a slot of 57 bits for future expansion. We restrict the value supported in
linux kernel 51 bits, so that we can use the bits between 57-51 for storing
hash linux page table bits. This is done in the next patch.
This will free up the software page table bits to be used for features
that are needed for both hash and radix. The current hash linux page table
format doesn't have any free software bits. Moving hash linux page table
specific bits to top of RPN field free up the software bits for other purpose.
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
---
arch/powerpc/include/asm/book3s/64/pgtable.h | 24 ++++++++++++++++++++++--
1 file changed, 22 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/include/asm/book3s/64/pgtable.h b/arch/powerpc/include/asm/book3s/64/pgtable.h
index dec136742cd7..f1381f85c00a 100644
--- a/arch/powerpc/include/asm/book3s/64/pgtable.h
+++ b/arch/powerpc/include/asm/book3s/64/pgtable.h
@@ -32,6 +32,25 @@
#define _RPAGE_RSV4 0x0200000000000000UL
#define _RPAGE_RPN0 0x01000
#define _RPAGE_RPN1 0x02000
+/* Max physicall address bit as per radix table */
+#define _RPAGE_PA_MAX 57
+/*
+ * Max physical address bit we will use for now.
+ *
+ * This is mostly a hardware limitation and for now Power9 has
+ * a 51 bit limit.
+ *
+ * This is different from the number of physical bit required to address
+ * the last byte of memory. That is defined by MAX_PHYSMEM_BITS.
+ * MAX_PHYSMEM_BITS is a linux limitation imposed by the maximum
+ * number of sections we can support (SECTIONS_SHIFT).
+ *
+ * This is different from Radix page table limitation above and
+ * should always be less than that. The limit is done such that
+ * we can overload the bits between _RPAGE_PA_MAX and _PAGE_PA_MAX
+ * for hash linux page table specific bits.
+ */
+#define _PAGE_PA_MAX 51
#define _PAGE_SOFT_DIRTY _RPAGE_SW3 /* software: software dirty tracking */
#define _PAGE_SPECIAL _RPAGE_SW2 /* software: special page */
@@ -45,10 +64,11 @@
*/
#define _PAGE_NO_CACHE _PAGE_TOLERANT
/*
- * We support 57 bit real address in pte. Clear everything above 57, and
+ * We support _RPAGE_PA_MAX bit real address in pte. On the linux side
+ * we are limited by _PAGE_PA_MAX. Clear everything above _PAGE_PA_MAX
* every thing below PAGE_SHIFT;
*/
-#define PTE_RPN_MASK (((1UL << 57) - 1) & (PAGE_MASK))
+#define PTE_RPN_MASK (((1UL << _PAGE_PA_MAX) - 1) & (PAGE_MASK))
/*
* set of bits not changed in pmd_modify. Even though we have hash specific bits
* in here, on radix we expect them to be zero.
--
2.7.4
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH 4/5] powerpc/mm/radix: Make max pfn bits a variable
2017-02-21 8:19 [PATCH 1/5] powerpc/mm: Conditional defines of pte bits are messy Aneesh Kumar K.V
2017-02-21 8:19 ` [PATCH 2/5] powerpc/mm: Express everything based on Radix page table defines Aneesh Kumar K.V
2017-02-21 8:19 ` [PATCH 3/5] powerpc/mm: Lower the max real address to 51 bits Aneesh Kumar K.V
@ 2017-02-21 8:19 ` Aneesh Kumar K.V
2017-02-21 8:19 ` [PATCH 5/5] powerpc/mm: Move hash specific pte bits to be top bits of RPN Aneesh Kumar K.V
3 siblings, 0 replies; 5+ messages in thread
From: Aneesh Kumar K.V @ 2017-02-21 8:19 UTC (permalink / raw)
To: benh, paulus, mpe; +Cc: linuxppc-dev, Aneesh Kumar K.V
This makes max pysical address bits a variable so that hash and radix
translation mode can choose what value to use. In this patch we also switch the
radix translation mode to use 57 bits. This make it resilient to future changes
to max pfn supported by platforms.
Tis patch is split from the previous one to make the review easier.
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
---
arch/powerpc/include/asm/book3s/64/hash.h | 18 ++++++++++++++++++
arch/powerpc/include/asm/book3s/64/pgtable.h | 28 +++++-----------------------
arch/powerpc/include/asm/book3s/64/radix.h | 4 ++++
arch/powerpc/mm/hash_utils_64.c | 1 +
arch/powerpc/mm/pgtable-radix.c | 1 +
arch/powerpc/mm/pgtable_64.c | 3 +++
6 files changed, 32 insertions(+), 23 deletions(-)
diff --git a/arch/powerpc/include/asm/book3s/64/hash.h b/arch/powerpc/include/asm/book3s/64/hash.h
index ec2828b1db07..af3c88624d3a 100644
--- a/arch/powerpc/include/asm/book3s/64/hash.h
+++ b/arch/powerpc/include/asm/book3s/64/hash.h
@@ -20,6 +20,24 @@
#define H_PAGE_F_GIX (_RPAGE_RSV2 | _RPAGE_RSV3 | _RPAGE_RSV4)
#define H_PAGE_F_SECOND _RPAGE_RSV1 /* HPTE is in 2ndary HPTEG */
#define H_PAGE_HASHPTE _RPAGE_SW0 /* PTE has associated HPTE */
+/*
+ * Max physical address bit we will use for now.
+ *
+ * This is mostly a hardware limitation and for now Power9 has
+ * a 51 bit limit.
+ *
+ * This is different from the number of physical bit required to address
+ * the last byte of memory. That is defined by MAX_PHYSMEM_BITS.
+ * MAX_PHYSMEM_BITS is a linux limitation imposed by the maximum
+ * number of sections we can support (SECTIONS_SHIFT).
+ *
+ * This is different from Radix page table limitation and
+ * should always be less than that. The limit is done such that
+ * we can overload the bits between _RPAGE_PA_MAX and H_PAGE_PA_MAX
+ * for hash linux page table specific bits.
+ */
+#define H_PAGE_PA_MAX 51
+#define H_PTE_RPN_MASK (((1UL << H_PAGE_PA_MAX) - 1) & (PAGE_MASK))
#ifdef CONFIG_PPC_64K_PAGES
#include <asm/book3s/64/hash-64k.h>
diff --git a/arch/powerpc/include/asm/book3s/64/pgtable.h b/arch/powerpc/include/asm/book3s/64/pgtable.h
index f1381f85c00a..0ea69c91520b 100644
--- a/arch/powerpc/include/asm/book3s/64/pgtable.h
+++ b/arch/powerpc/include/asm/book3s/64/pgtable.h
@@ -34,23 +34,6 @@
#define _RPAGE_RPN1 0x02000
/* Max physicall address bit as per radix table */
#define _RPAGE_PA_MAX 57
-/*
- * Max physical address bit we will use for now.
- *
- * This is mostly a hardware limitation and for now Power9 has
- * a 51 bit limit.
- *
- * This is different from the number of physical bit required to address
- * the last byte of memory. That is defined by MAX_PHYSMEM_BITS.
- * MAX_PHYSMEM_BITS is a linux limitation imposed by the maximum
- * number of sections we can support (SECTIONS_SHIFT).
- *
- * This is different from Radix page table limitation above and
- * should always be less than that. The limit is done such that
- * we can overload the bits between _RPAGE_PA_MAX and _PAGE_PA_MAX
- * for hash linux page table specific bits.
- */
-#define _PAGE_PA_MAX 51
#define _PAGE_SOFT_DIRTY _RPAGE_SW3 /* software: software dirty tracking */
#define _PAGE_SPECIAL _RPAGE_SW2 /* software: special page */
@@ -64,12 +47,6 @@
*/
#define _PAGE_NO_CACHE _PAGE_TOLERANT
/*
- * We support _RPAGE_PA_MAX bit real address in pte. On the linux side
- * we are limited by _PAGE_PA_MAX. Clear everything above _PAGE_PA_MAX
- * every thing below PAGE_SHIFT;
- */
-#define PTE_RPN_MASK (((1UL << _PAGE_PA_MAX) - 1) & (PAGE_MASK))
-/*
* set of bits not changed in pmd_modify. Even though we have hash specific bits
* in here, on radix we expect them to be zero.
*/
@@ -174,6 +151,11 @@
#ifndef __ASSEMBLY__
/*
+ * based on max physical address bit that we want to encode in page table
+ */
+extern unsigned long __pte_rpn_mask;
+#define PTE_RPN_MASK __pte_rpn_mask
+/*
* page table defines
*/
extern unsigned long __pte_index_size;
diff --git a/arch/powerpc/include/asm/book3s/64/radix.h b/arch/powerpc/include/asm/book3s/64/radix.h
index 96b94d2b4432..d4ab838b97b2 100644
--- a/arch/powerpc/include/asm/book3s/64/radix.h
+++ b/arch/powerpc/include/asm/book3s/64/radix.h
@@ -24,6 +24,10 @@
/* An empty PTE can still have a R or C writeback */
#define RADIX_PTE_NONE_MASK (_PAGE_DIRTY | _PAGE_ACCESSED)
+/*
+ * Clear everything above _RPAGE_PA_MAX every thing below PAGE_SHIFT
+ */
+#define RADIX_PTE_RPN_MASK (((1UL << _RPAGE_PA_MAX) - 1) & (PAGE_MASK))
/* Bits to set in a RPMD/RPUD/RPGD */
#define RADIX_PMD_VAL_BITS (0x8000000000000000UL | RADIX_PTE_INDEX_SIZE)
diff --git a/arch/powerpc/mm/hash_utils_64.c b/arch/powerpc/mm/hash_utils_64.c
index 67e19a0821be..edcca1628bbf 100644
--- a/arch/powerpc/mm/hash_utils_64.c
+++ b/arch/powerpc/mm/hash_utils_64.c
@@ -955,6 +955,7 @@ void __init hash__early_init_mmu(void)
/*
* initialize page table size
*/
+ __pte_rpn_mask = H_PTE_RPN_MASK;
__pte_frag_nr = H_PTE_FRAG_NR;
__pte_frag_size_shift = H_PTE_FRAG_SIZE_SHIFT;
diff --git a/arch/powerpc/mm/pgtable-radix.c b/arch/powerpc/mm/pgtable-radix.c
index 34f1a0dbc898..b5b8d695fdee 100644
--- a/arch/powerpc/mm/pgtable-radix.c
+++ b/arch/powerpc/mm/pgtable-radix.c
@@ -362,6 +362,7 @@ void __init radix__early_init_mmu(void)
/*
* initialize page table size
*/
+ __pte_rpn_mask = RADIX_PTE_RPN_MASK;
__pte_index_size = RADIX_PTE_INDEX_SIZE;
__pmd_index_size = RADIX_PMD_INDEX_SIZE;
__pud_index_size = RADIX_PUD_INDEX_SIZE;
diff --git a/arch/powerpc/mm/pgtable_64.c b/arch/powerpc/mm/pgtable_64.c
index 8bca7f58afc4..c9f5420a93f7 100644
--- a/arch/powerpc/mm/pgtable_64.c
+++ b/arch/powerpc/mm/pgtable_64.c
@@ -67,6 +67,9 @@
*/
struct prtb_entry *process_tb;
struct patb_entry *partition_tb;
+
+unsigned long __pte_rpn_mask;
+EXPORT_SYMBOL(__pte_rpn_mask);
/*
* page table size
*/
--
2.7.4
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH 5/5] powerpc/mm: Move hash specific pte bits to be top bits of RPN
2017-02-21 8:19 [PATCH 1/5] powerpc/mm: Conditional defines of pte bits are messy Aneesh Kumar K.V
` (2 preceding siblings ...)
2017-02-21 8:19 ` [PATCH 4/5] powerpc/mm/radix: Make max pfn bits a variable Aneesh Kumar K.V
@ 2017-02-21 8:19 ` Aneesh Kumar K.V
3 siblings, 0 replies; 5+ messages in thread
From: Aneesh Kumar K.V @ 2017-02-21 8:19 UTC (permalink / raw)
To: benh, paulus, mpe; +Cc: linuxppc-dev, Aneesh Kumar K.V
We don't support the full 57 bits of physical address and hence can overload
the top bits of RPN as hash specific pte bits.
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
---
arch/powerpc/include/asm/book3s/64/hash.h | 18 ++++++------------
arch/powerpc/include/asm/book3s/64/pgtable.h | 19 ++++++++++++++++---
2 files changed, 22 insertions(+), 15 deletions(-)
diff --git a/arch/powerpc/include/asm/book3s/64/hash.h b/arch/powerpc/include/asm/book3s/64/hash.h
index af3c88624d3a..205c04df9cf3 100644
--- a/arch/powerpc/include/asm/book3s/64/hash.h
+++ b/arch/powerpc/include/asm/book3s/64/hash.h
@@ -6,20 +6,14 @@
* Common bits between 4K and 64K pages in a linux-style PTE.
* Additional bits may be defined in pgtable-hash64-*.h
*
- * Note: We only support user read/write permissions. Supervisor always
- * have full read/write to pages above PAGE_OFFSET (pages below that
- * always use the user access permissions).
- *
- * We could create separate kernel read-only if we used the 3 PP bits
- * combinations that newer processors provide but we currently don't.
*/
-#define H_PAGE_BUSY _RPAGE_SW1 /* software: PTE & hash are busy */
+#define H_PAGE_BUSY _RPAGE_RPN45 /* software: PTE & hash are busy */
#define H_PTE_NONE_MASK _PAGE_HPTEFLAGS
-#define H_PAGE_F_GIX_SHIFT 57
-/* (7ul << 57) HPTE index within HPTEG */
-#define H_PAGE_F_GIX (_RPAGE_RSV2 | _RPAGE_RSV3 | _RPAGE_RSV4)
-#define H_PAGE_F_SECOND _RPAGE_RSV1 /* HPTE is in 2ndary HPTEG */
-#define H_PAGE_HASHPTE _RPAGE_SW0 /* PTE has associated HPTE */
+#define H_PAGE_F_GIX_SHIFT 53
+/* (7ul << 53) HPTE index within HPTEG */
+#define H_PAGE_F_GIX (_RPAGE_RPN44 | _RPAGE_RPN43 | _RPAGE_RPN42)
+#define H_PAGE_F_SECOND _RPAGE_RPN41 /* HPTE is in 2ndary HPTEG */
+#define H_PAGE_HASHPTE _RPAGE_RPN40 /* PTE has associated HPTE */
/*
* Max physical address bit we will use for now.
*
diff --git a/arch/powerpc/include/asm/book3s/64/pgtable.h b/arch/powerpc/include/asm/book3s/64/pgtable.h
index 0ea69c91520b..3fd9e46e44c5 100644
--- a/arch/powerpc/include/asm/book3s/64/pgtable.h
+++ b/arch/powerpc/include/asm/book3s/64/pgtable.h
@@ -30,16 +30,29 @@
#define _RPAGE_RSV2 0x0800000000000000UL
#define _RPAGE_RSV3 0x0400000000000000UL
#define _RPAGE_RSV4 0x0200000000000000UL
+
+#define _PAGE_PTE 0x4000000000000000UL /* distinguishes PTEs from pointers */
+#define _PAGE_PRESENT 0x8000000000000000UL /* pte contains a translation */
+
+/*
+ * Top and bottom bits of RPN which can be used by hash
+ * translation mode, because we expect them to be zero
+ * otherwise.
+ */
#define _RPAGE_RPN0 0x01000
#define _RPAGE_RPN1 0x02000
+#define _RPAGE_RPN45 0x0100000000000000UL
+#define _RPAGE_RPN44 0x0080000000000000UL
+#define _RPAGE_RPN43 0x0040000000000000UL
+#define _RPAGE_RPN42 0x0020000000000000UL
+#define _RPAGE_RPN41 0x0010000000000000UL
+#define _RPAGE_RPN40 0x0008000000000000UL
+
/* Max physicall address bit as per radix table */
#define _RPAGE_PA_MAX 57
#define _PAGE_SOFT_DIRTY _RPAGE_SW3 /* software: software dirty tracking */
#define _PAGE_SPECIAL _RPAGE_SW2 /* software: special page */
-
-#define _PAGE_PTE 0x4000000000000000UL /* distinguishes PTEs from pointers */
-#define _PAGE_PRESENT 0x8000000000000000UL /* pte contains a translation */
/*
* Drivers request for cache inhibited pte mapping using _PAGE_NO_CACHE
* Instead of fixing all of them, add an alternate define which
--
2.7.4
^ permalink raw reply related [flat|nested] 5+ messages in thread