From: "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com>
To: benh@kernel.crashing.org, paulus@samba.org, mpe@ellerman.id.au
Cc: linuxppc-dev@lists.ozlabs.org,
"Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com>
Subject: [PATCH V2 03/11] powerpc/mm: Cleanup bits definition between hash and radix.
Date: Thu, 16 Mar 2017 16:02:01 +0530 [thread overview]
Message-ID: <1489660329-22501-4-git-send-email-aneesh.kumar@linux.vnet.ibm.com> (raw)
In-Reply-To: <1489660329-22501-1-git-send-email-aneesh.kumar@linux.vnet.ibm.com>
Define everything based on bits present in pgtable.h. This will help in easily
identifying overlapping bits between hash/radix.
No functional change with this patch.
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
---
arch/powerpc/include/asm/book3s/64/hash-64k.h | 4 ++++
arch/powerpc/include/asm/book3s/64/hash.h | 9 +++++----
arch/powerpc/include/asm/book3s/64/pgtable.h | 10 ++--------
arch/powerpc/include/asm/book3s/64/radix.h | 6 ++++++
4 files changed, 17 insertions(+), 12 deletions(-)
diff --git a/arch/powerpc/include/asm/book3s/64/hash-64k.h b/arch/powerpc/include/asm/book3s/64/hash-64k.h
index f3dd21efa2ea..b39f0b86405e 100644
--- a/arch/powerpc/include/asm/book3s/64/hash-64k.h
+++ b/arch/powerpc/include/asm/book3s/64/hash-64k.h
@@ -6,6 +6,10 @@
#define H_PUD_INDEX_SIZE 5
#define H_PGD_INDEX_SIZE 12
+/*
+ * 64k aligned address free up few of the lower bits of RPN for us
+ * We steal that here. For more deatils look at pte_pfn/pfn_pte()
+ */
#define H_PAGE_COMBO 0x00001000 /* this is a combo 4k page */
#define H_PAGE_4K_PFN 0x00002000 /* PFN is for a single 4k page */
/*
diff --git a/arch/powerpc/include/asm/book3s/64/hash.h b/arch/powerpc/include/asm/book3s/64/hash.h
index f7b721bbf918..ec2828b1db07 100644
--- a/arch/powerpc/include/asm/book3s/64/hash.h
+++ b/arch/powerpc/include/asm/book3s/64/hash.h
@@ -13,12 +13,13 @@
* We could create separate kernel read-only if we used the 3 PP bits
* combinations that newer processors provide but we currently don't.
*/
-#define H_PAGE_BUSY 0x00800 /* software: PTE & hash are busy */
+#define H_PAGE_BUSY _RPAGE_SW1 /* software: PTE & hash are busy */
#define H_PTE_NONE_MASK _PAGE_HPTEFLAGS
#define H_PAGE_F_GIX_SHIFT 57
-#define H_PAGE_F_GIX (7ul << 57) /* HPTE index within HPTEG */
-#define H_PAGE_F_SECOND (1ul << 60) /* HPTE is in 2ndary HPTEG */
-#define H_PAGE_HASHPTE (1ul << 61) /* PTE has associated HPTE */
+/* (7ul << 57) HPTE index within HPTEG */
+#define H_PAGE_F_GIX (_RPAGE_RSV2 | _RPAGE_RSV3 | _RPAGE_RSV4)
+#define H_PAGE_F_SECOND _RPAGE_RSV1 /* HPTE is in 2ndary HPTEG */
+#define H_PAGE_HASHPTE _RPAGE_SW0 /* PTE has associated HPTE */
#ifdef CONFIG_PPC_64K_PAGES
#include <asm/book3s/64/hash-64k.h>
diff --git a/arch/powerpc/include/asm/book3s/64/pgtable.h b/arch/powerpc/include/asm/book3s/64/pgtable.h
index 8f4d41936e5a..c39bc4cb9247 100644
--- a/arch/powerpc/include/asm/book3s/64/pgtable.h
+++ b/arch/powerpc/include/asm/book3s/64/pgtable.h
@@ -44,14 +44,8 @@
#endif
#define _PAGE_SPECIAL _RPAGE_SW2 /* software: special page */
-/*
- * For P9 DD1 only, we need to track whether the pte's huge.
- */
-#define _PAGE_LARGE _RPAGE_RSV1
-
-
-#define _PAGE_PTE (1ul << 62) /* distinguishes PTEs from pointers */
-#define _PAGE_PRESENT (1ul << 63) /* pte contains a translation */
+#define _PAGE_PTE 0x4000000000000000UL /* distinguishes PTEs from pointers */
+#define _PAGE_PRESENT 0x8000000000000000UL /* pte contains a translation */
/*
* Drivers request for cache inhibited pte mapping using _PAGE_NO_CACHE
* Instead of fixing all of them, add an alternate define which
diff --git a/arch/powerpc/include/asm/book3s/64/radix.h b/arch/powerpc/include/asm/book3s/64/radix.h
index 9e0bb7cd6e22..2a2ea47a9bd2 100644
--- a/arch/powerpc/include/asm/book3s/64/radix.h
+++ b/arch/powerpc/include/asm/book3s/64/radix.h
@@ -11,6 +11,12 @@
#include <asm/book3s/64/radix-4k.h>
#endif
+/*
+ * For P9 DD1 only, we need to track whether the pte's huge.
+ */
+#define _PAGE_LARGE _RPAGE_RSV1
+
+
#ifndef __ASSEMBLY__
#include <asm/book3s/64/tlbflush-radix.h>
#include <asm/cpu_has_feature.h>
--
2.7.4
next prev parent reply other threads:[~2017-03-16 10:32 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-03-16 10:31 [PATCH V2 00/11] powerpc/mm/hash: Cleanup and fixes Aneesh Kumar K.V
2017-03-16 10:31 ` [PATCH V2 01/11] powerpc/mm/nohash: MM_SLICE is only used by book3s 64 Aneesh Kumar K.V
2017-03-16 22:00 ` Paul Mackerras
2017-03-16 10:32 ` [PATCH V2 02/11] powerpc/mm/slice: when computing slice mask limit lowe slice max addr correctly Aneesh Kumar K.V
2017-03-16 22:03 ` Paul Mackerras
2017-03-17 6:55 ` Aneesh Kumar K.V
2017-03-16 10:32 ` Aneesh Kumar K.V [this message]
2017-03-16 22:16 ` [PATCH V2 03/11] powerpc/mm: Cleanup bits definition between hash and radix Paul Mackerras
2017-03-16 10:32 ` [PATCH V2 04/11] powerpc/mm/radix: rename _PAGE_LARGE to R_PAGE_LARGE Aneesh Kumar K.V
2017-03-16 22:16 ` Paul Mackerras
2017-03-16 10:32 ` [PATCH V2 05/11] powerpc/mm: Add translation mode information in /proc/cpuinfo Aneesh Kumar K.V
2017-03-16 22:17 ` Paul Mackerras
2017-03-16 10:32 ` [PATCH V2 06/11] powerpc/mm/hugetlb: Filter out hugepage size not supported by page table layout Aneesh Kumar K.V
2017-03-16 22:19 ` Paul Mackerras
2017-03-16 10:32 ` [PATCH V2 07/11] powerpc/mm: Conditional defines of pte bits are messy Aneesh Kumar K.V
2017-03-16 22:21 ` Paul Mackerras
2017-03-16 10:32 ` [PATCH V2 08/11] powerpc/mm: Express everything based on Radix page table defines Aneesh Kumar K.V
2017-03-16 22:24 ` Paul Mackerras
2017-03-16 10:32 ` [PATCH V2 09/11] powerpc/mm: Lower the max real address to 51 bits Aneesh Kumar K.V
2017-03-16 21:26 ` Benjamin Herrenschmidt
2017-03-17 3:39 ` Aneesh Kumar K.V
2017-03-16 22:27 ` Paul Mackerras
2017-03-16 10:32 ` [PATCH V2 10/11] powerpc/mm/radix: Make max pfn bits a variable Aneesh Kumar K.V
2017-03-16 22:29 ` Paul Mackerras
2017-03-17 8:54 ` Aneesh Kumar K.V
2017-03-16 10:32 ` [PATCH V2 11/11] powerpc/mm: Move hash specific pte bits to be top bits of RPN Aneesh Kumar K.V
2017-03-16 22:34 ` Paul Mackerras
2017-03-17 3:37 ` Aneesh Kumar K.V
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1489660329-22501-4-git-send-email-aneesh.kumar@linux.vnet.ibm.com \
--to=aneesh.kumar@linux.vnet.ibm.com \
--cc=benh@kernel.crashing.org \
--cc=linuxppc-dev@lists.ozlabs.org \
--cc=mpe@ellerman.id.au \
--cc=paulus@samba.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).