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From: Andrew Donnellan <ajd@linux.ibm.com>
To: Frederic Barrat <fbarrat@linux.ibm.com>,
	linuxppc-dev@lists.ozlabs.org, clombard@linux.ibm.com,
	alastair@au1.ibm.com
Subject: Re: [PATCH v5] ocxl: control via sysfs whether the FPGA is reloaded on a link reset
Date: Fri, 3 Jul 2020 02:55:55 +1000	[thread overview]
Message-ID: <148b2a1b-d0c9-6fb3-f4fd-d9fbd61a473f@linux.ibm.com> (raw)
In-Reply-To: <20200619140439.153962-1-fbarrat@linux.ibm.com>

On 20/6/20 12:04 am, Frederic Barrat wrote:
> From: Philippe Bergheaud <felix@linux.ibm.com>
> 
> Some opencapi FPGA images allow to control if the FPGA should be reloaded
> on the next adapter reset. If it is supported, the image specifies it
> through a Vendor Specific DVSEC in the config space of function 0.
> 
> Signed-off-by: Philippe Bergheaud <felix@linux.ibm.com>
> Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Reviewed-by: Andrew Donnellan <ajd@linux.ibm.com>

-- 
Andrew Donnellan              OzLabs, ADL Canberra
ajd@linux.ibm.com             IBM Australia Limited

  reply	other threads:[~2020-07-02 17:00 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-06-19 14:04 [PATCH v5] ocxl: control via sysfs whether the FPGA is reloaded on a link reset Frederic Barrat
2020-07-02 16:55 ` Andrew Donnellan [this message]
2020-07-16 12:55 ` Michael Ellerman

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