From: "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com>
To: benh@kernel.crashing.org, paulus@samba.org, mpe@ellerman.id.au
Cc: linuxppc-dev@lists.ozlabs.org,
"Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com>
Subject: [PATCH V5 11/17] powerpc/mm/hash: Increase VA range to 128TB
Date: Wed, 22 Mar 2017 09:06:57 +0530 [thread overview]
Message-ID: <1490153823-29241-12-git-send-email-aneesh.kumar@linux.vnet.ibm.com> (raw)
In-Reply-To: <1490153823-29241-1-git-send-email-aneesh.kumar@linux.vnet.ibm.com>
We update the hash linux page table layout such that we can support 512TB. But
we limit the TASK_SIZE to 128TB. We can switch to 128TB by default without
conditional because that is the max virtual address supported by other
architectures. We will later add a mechanism to on-demand increase the
application's effective address range to 512TB.
Having the page table layout changed to accommodate 512TB makes testing large
memory configuration easier with less code changes to kernel
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
---
arch/powerpc/include/asm/book3s/64/hash-4k.h | 2 +-
arch/powerpc/include/asm/book3s/64/hash-64k.h | 2 +-
arch/powerpc/include/asm/processor.h | 22 ++++++++++++++++++----
3 files changed, 20 insertions(+), 6 deletions(-)
diff --git a/arch/powerpc/include/asm/book3s/64/hash-4k.h b/arch/powerpc/include/asm/book3s/64/hash-4k.h
index 0c4e470571ca..b4b5e6b671ca 100644
--- a/arch/powerpc/include/asm/book3s/64/hash-4k.h
+++ b/arch/powerpc/include/asm/book3s/64/hash-4k.h
@@ -8,7 +8,7 @@
#define H_PTE_INDEX_SIZE 9
#define H_PMD_INDEX_SIZE 7
#define H_PUD_INDEX_SIZE 9
-#define H_PGD_INDEX_SIZE 9
+#define H_PGD_INDEX_SIZE 12
#ifndef __ASSEMBLY__
#define H_PTE_TABLE_SIZE (sizeof(pte_t) << H_PTE_INDEX_SIZE)
diff --git a/arch/powerpc/include/asm/book3s/64/hash-64k.h b/arch/powerpc/include/asm/book3s/64/hash-64k.h
index 7be54f9590a3..214219dff87c 100644
--- a/arch/powerpc/include/asm/book3s/64/hash-64k.h
+++ b/arch/powerpc/include/asm/book3s/64/hash-64k.h
@@ -4,7 +4,7 @@
#define H_PTE_INDEX_SIZE 8
#define H_PMD_INDEX_SIZE 5
#define H_PUD_INDEX_SIZE 5
-#define H_PGD_INDEX_SIZE 12
+#define H_PGD_INDEX_SIZE 15
/*
* 64k aligned address free up few of the lower bits of RPN for us
diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h
index e0fecbcea2a2..146c3a91d89f 100644
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@@ -102,11 +102,25 @@ void release_thread(struct task_struct *);
#endif
#ifdef CONFIG_PPC64
-/* 64-bit user address space is 46-bits (64TB user VM) */
-#define TASK_SIZE_USER64 (0x0000400000000000UL)
+/*
+ * 64-bit user address space can have multiple limits
+ * For now supported values are:
+ */
+#define TASK_SIZE_64TB (0x0000400000000000UL)
+#define TASK_SIZE_128TB (0x0000800000000000UL)
+#define TASK_SIZE_512TB (0x0002000000000000UL)
-/*
- * 32-bit user address space is 4GB - 1 page
+#ifdef CONFIG_PPC_BOOK3S_64
+/*
+ * MAx value currently used:
+ */
+#define TASK_SIZE_USER64 TASK_SIZE_128TB
+#else
+#define TASK_SIZE_USER64 TASK_SIZE_64TB
+#endif
+
+/*
+ * 32-bit user address space is 4GB - 1 page
* (this 1 page is needed so referencing of 0xFFFFFFFF generates EFAULT
*/
#define TASK_SIZE_USER32 (0x0000000100000000UL - (1*PAGE_SIZE))
--
2.7.4
next prev parent reply other threads:[~2017-03-22 3:38 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-03-22 3:36 [PATCH V5 00/17] powerpc/mm/ppc64: Add 128TB support Aneesh Kumar K.V
2017-03-22 3:36 ` [PATCH V5 01/17] powerpc/mm/slice: Convert slice_mask high slice to a bitmap Aneesh Kumar K.V
2017-03-29 3:11 ` Paul Mackerras
2017-03-29 5:20 ` Aneesh Kumar K.V
2017-03-22 3:36 ` [PATCH V5 02/17] powerpc/mm/slice: Update the function prototype Aneesh Kumar K.V
2017-03-29 3:43 ` Paul Mackerras
2017-03-29 10:48 ` Aneesh Kumar K.V
2017-03-22 3:36 ` [PATCH V5 03/17] powerpc/mm: Move copy_mm_to_paca to paca.c Aneesh Kumar K.V
2017-03-22 3:36 ` [PATCH V5 04/17] powerpc/mm: Remove redundant TASK_SIZE_USER64 checks Aneesh Kumar K.V
2017-03-29 3:34 ` Michael Ellerman
2017-03-22 3:36 ` [PATCH V5 05/17] powerpc/mm/slice: Move slice_mask struct definition to slice.c Aneesh Kumar K.V
2017-03-22 3:36 ` [PATCH V5 06/17] powerpc/mm/slice: Update slice mask printing to use bitmap printing Aneesh Kumar K.V
2017-03-22 3:36 ` [PATCH V5 07/17] powerpc/mm/hash: Move kernel context to the starting of context range Aneesh Kumar K.V
2017-03-22 3:36 ` [PATCH V5 08/17] powerpc/mm/hash: Support 68 bit VA Aneesh Kumar K.V
2017-03-22 3:36 ` [PATCH V5 09/17] powerpc/mm/hash: VSID 0 is no more an invalid VSID Aneesh Kumar K.V
2017-03-22 3:36 ` [PATCH V5 10/17] powerpc/mm/hash: Convert mask to unsigned long Aneesh Kumar K.V
2017-03-22 3:36 ` Aneesh Kumar K.V [this message]
2017-03-22 3:36 ` [PATCH V5 12/17] powerpc/mm/slice: Use mm task_size as max value of slice index Aneesh Kumar K.V
2017-03-22 3:36 ` [PATCH V5 13/17] powerpc/mm/hash: Store task size in PACA Aneesh Kumar K.V
2017-03-22 3:37 ` [PATCH V5 14/17] powerpc/mm/hash: Skip using reserved virtual address range Aneesh Kumar K.V
2017-03-22 3:37 ` [PATCH V5 15/17] powerpc/mm: Switch TASK_SIZE check to use mm->task_size Aneesh Kumar K.V
2017-03-22 3:37 ` [PATCH V5 16/17] mm: Let arch choose the initial value of task size Aneesh Kumar K.V
2017-03-28 11:17 ` Michael Ellerman
2017-03-28 15:22 ` Aneesh Kumar K.V
2017-03-29 9:20 ` Anshuman Khandual
2017-03-30 3:03 ` Anshuman Khandual
2017-03-22 3:37 ` [PATCH V5 17/17] powerpc/mm: Enable mappings above 128TB Aneesh Kumar K.V
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