From: Christophe Lombard <clombard@linux.vnet.ibm.com>
To: linuxppc-dev@lists.ozlabs.org, fbarrat@linux.vnet.ibm.com,
imunsie@au1.ibm.com, andrew.donnellan@au1.ibm.com
Subject: [PATCH V3 2/7] cxl: Remove unused values in bare-metal environment.
Date: Tue, 28 Mar 2017 17:14:07 +0200 [thread overview]
Message-ID: <1490714052-18902-3-git-send-email-clombard@linux.vnet.ibm.com> (raw)
In-Reply-To: <1490714052-18902-1-git-send-email-clombard@linux.vnet.ibm.com>
The two fields pid and tid of the structure cxl_irq_info are only used
in the guest environment. To avoid confusion, it's not necessary
to fill the fields in the bare-metal environment. These two fields
are renamed to 'reserved' to avoid undefined behavior on bare-metal.
The PSL Process and Thread Identification Register (CXL_PSL_PID_TID_An)
is only used when attaching a dedicated process for PSL8 only. This
register goes away in CAIA2.
Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com>
---
drivers/misc/cxl/cxl.h | 13 +++++++------
drivers/misc/cxl/hcalls.c | 4 ++--
drivers/misc/cxl/native.c | 5 -----
3 files changed, 9 insertions(+), 13 deletions(-)
diff --git a/drivers/misc/cxl/cxl.h b/drivers/misc/cxl/cxl.h
index 79e60ec..2bbe077 100644
--- a/drivers/misc/cxl/cxl.h
+++ b/drivers/misc/cxl/cxl.h
@@ -895,19 +895,20 @@ int __detach_context(struct cxl_context *ctx);
* plpar_hcall9() in hvCall.S
* As a consequence:
* - we don't need to do any endianness conversion
- * - the pid and tid are an exception. They are 32-bit values returned in
- * the same 64-bit register. So we do need to worry about byte ordering.
+ * - the pid (reserved0) and tid (reserved1) are an exception. They are
+ * 32-bit values returned in the same 64-bit register. So we do need
+ * to worry about byte ordering.
*/
struct cxl_irq_info {
u64 dsisr;
u64 dar;
u64 dsr;
#ifndef CONFIG_CPU_LITTLE_ENDIAN
- u32 pid;
- u32 tid;
+ u32 reserved0;
+ u32 reserved1;
#else
- u32 tid;
- u32 pid;
+ u32 reserved1;
+ u32 reserved0;
#endif
u64 afu_err;
u64 errstat;
diff --git a/drivers/misc/cxl/hcalls.c b/drivers/misc/cxl/hcalls.c
index d6d11f4..142a095 100644
--- a/drivers/misc/cxl/hcalls.c
+++ b/drivers/misc/cxl/hcalls.c
@@ -414,8 +414,8 @@ long cxl_h_collect_int_info(u64 unit_address, u64 process_token,
switch (rc) {
case H_SUCCESS: /* The interrupt info is returned in return registers. */
pr_devel("dsisr:%#llx, dar:%#llx, dsr:%#llx, pid:%u, tid:%u, afu_err:%#llx, errstat:%#llx\n",
- info->dsisr, info->dar, info->dsr, info->pid,
- info->tid, info->afu_err, info->errstat);
+ info->dsisr, info->dar, info->dsr, info->reserved0,
+ info->reserved1, info->afu_err, info->errstat);
return 0;
case H_PARAMETER: /* An incorrect parameter was supplied. */
return -EINVAL;
diff --git a/drivers/misc/cxl/native.c b/drivers/misc/cxl/native.c
index 7ae7105..7257e8b 100644
--- a/drivers/misc/cxl/native.c
+++ b/drivers/misc/cxl/native.c
@@ -859,8 +859,6 @@ static int native_detach_process(struct cxl_context *ctx)
static int native_get_irq_info(struct cxl_afu *afu, struct cxl_irq_info *info)
{
- u64 pidtid;
-
/* If the adapter has gone away, we can't get any meaningful
* information.
*/
@@ -870,9 +868,6 @@ static int native_get_irq_info(struct cxl_afu *afu, struct cxl_irq_info *info)
info->dsisr = cxl_p2n_read(afu, CXL_PSL_DSISR_An);
info->dar = cxl_p2n_read(afu, CXL_PSL_DAR_An);
info->dsr = cxl_p2n_read(afu, CXL_PSL_DSR_An);
- pidtid = cxl_p2n_read(afu, CXL_PSL_PID_TID_An);
- info->pid = pidtid >> 32;
- info->tid = pidtid & 0xffffffff;
info->afu_err = cxl_p2n_read(afu, CXL_AFU_ERR_An);
info->errstat = cxl_p2n_read(afu, CXL_PSL_ErrStat_An);
info->proc_handle = 0;
--
2.7.4
next prev parent reply other threads:[~2017-03-28 15:14 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-03-28 15:14 [PATCH V3 0/7] cxl: Add support for Coherent Accelerator Interface Architecture 2.0 Christophe Lombard
2017-03-28 15:14 ` [PATCH V3 1/7] cxl: Read vsec perst load image Christophe Lombard
2017-03-28 23:51 ` Andrew Donnellan
2017-04-03 12:23 ` Frederic Barrat
2017-03-28 15:14 ` Christophe Lombard [this message]
2017-03-29 0:21 ` [PATCH V3 2/7] cxl: Remove unused values in bare-metal environment Andrew Donnellan
2017-03-29 15:53 ` christophe lombard
2017-04-03 12:27 ` Frederic Barrat
2017-04-05 9:34 ` christophe lombard
2017-03-28 15:14 ` [PATCH V3 3/7] cxl: Keep track of mm struct associated with a context Christophe Lombard
2017-03-29 2:58 ` Andrew Donnellan
2017-04-03 12:29 ` Frederic Barrat
2017-03-28 15:14 ` [PATCH V3 4/7] cxl: Update implementation service layer Christophe Lombard
2017-03-31 7:49 ` Andrew Donnellan
2017-04-03 12:39 ` Frederic Barrat
2017-04-05 12:34 ` christophe lombard
2017-03-28 15:14 ` [PATCH V3 5/7] cxl: Rename some psl8 specific functions Christophe Lombard
2017-03-31 7:55 ` Andrew Donnellan
2017-04-03 12:42 ` Frederic Barrat
2017-03-28 15:14 ` [PATCH V3 6/7] cxl: Isolate few psl8 specific calls Christophe Lombard
2017-04-03 12:53 ` Frederic Barrat
2017-03-28 15:14 ` [PATCH V3 7/7] cxl: Add psl9 specific code Christophe Lombard
2017-04-03 13:05 ` Frederic Barrat
2017-04-07 6:53 ` christophe lombard
2017-03-30 4:44 ` [PATCH V3 0/7] cxl: Add support for Coherent Accelerator Interface Architecture 2.0 Andrew Donnellan
2017-03-30 13:26 ` christophe lombard
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