From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx0a-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3w6ryt2pqzzDq9m for ; Wed, 19 Apr 2017 03:02:13 +1000 (AEST) Received: from pps.filterd (m0098414.ppops.net [127.0.0.1]) by mx0b-001b2d01.pphosted.com (8.16.0.20/8.16.0.20) with SMTP id v3IGwkuu011284 for ; Tue, 18 Apr 2017 13:02:08 -0400 Received: from e28smtp02.in.ibm.com (e28smtp02.in.ibm.com [125.16.236.2]) by mx0b-001b2d01.pphosted.com with ESMTP id 29w2eagn4j-1 (version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT) for ; Tue, 18 Apr 2017 13:02:08 -0400 Received: from localhost by e28smtp02.in.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Tue, 18 Apr 2017 22:32:04 +0530 Received: from d28av06.in.ibm.com (d28av06.in.ibm.com [9.184.220.48]) by d28relay02.in.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id v3IH21Vl18612440 for ; Tue, 18 Apr 2017 22:32:01 +0530 Received: from d28av06.in.ibm.com (localhost [127.0.0.1]) by d28av06.in.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id v3IH1w9x024613 for ; Tue, 18 Apr 2017 22:32:01 +0530 From: Anju T Sudhakar To: mpe@ellerman.id.au Cc: linux-kernel@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, ego@linux.vnet.ibm.com, bsingharora@gmail.com, benh@kernel.crashing.org, paulus@samba.org, anton@samba.org, sukadev@linux.vnet.ibm.com, mikey@neuling.org, stewart@linux.vnet.ibm.com, dja@axtens.net, eranian@google.com, hemant@linux.vnet.ibm.com, maddy@linux.vnet.ibm.com, anju@linux.vnet.ibm.com Subject: [PATCH v7 01/10] powerpc/powernv: Data structure and macros definitions for IMC Date: Tue, 18 Apr 2017 22:31:41 +0530 In-Reply-To: <1492534910-7991-1-git-send-email-anju@linux.vnet.ibm.com> References: <1492534910-7991-1-git-send-email-anju@linux.vnet.ibm.com> Message-Id: <1492534910-7991-2-git-send-email-anju@linux.vnet.ibm.com> List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , From: Hemant Kumar Create a new header file to add the data structures and macros needed for In-Memory Collection (IMC) counter support. Signed-off-by: Anju T Sudhakar Signed-off-by: Hemant Kumar Signed-off-by: Madhavan Srinivasan --- arch/powerpc/include/asm/imc-pmu.h | 95 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 95 insertions(+) create mode 100644 arch/powerpc/include/asm/imc-pmu.h diff --git a/arch/powerpc/include/asm/imc-pmu.h b/arch/powerpc/include/asm/imc-pmu.h new file mode 100644 index 0000000..d0193c8 --- /dev/null +++ b/arch/powerpc/include/asm/imc-pmu.h @@ -0,0 +1,95 @@ +#ifndef PPC_POWERNV_IMC_PMU_DEF_H +#define PPC_POWERNV_IMC_PMU_DEF_H + +/* + * IMC Nest Performance Monitor counter support. + * + * Copyright (C) 2017 Madhavan Srinivasan, IBM Corporation. + * (C) 2017 Anju T Sudhakar, IBM Corporation. + * (C) 2017 Hemant K Shaw, IBM Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include + +/* + * For static allocation of some of the structures. + */ +#define IMC_MAX_CHIPS 32 +#define IMC_MAX_PMUS 32 + +/* + * This macro is used for memory buffer allocation of + * event names and event string + */ +#define IMC_MAX_NAME_VAL_LEN 96 + +/* + * Currently Microcode supports a max of 256KB of counter memory + * in the reserved memory region. Max pages to mmap (considering 4K PAGESIZE). + */ +#define IMC_NEST_MAX_PAGES 64 + +/* + *Compatbility macros for IMC devices + */ +#define IMC_DTB_COMPAT "ibm,opal-in-memory-counters" +#define IMC_DTB_NEST_COMPAT "ibm,imc-counters-nest" + +/* + * Structure to hold per chip specific memory address + * information for nest pmus. Nest Counter data are exported + * in per-chip reserved memory region by the PORE Engine. + */ +struct perchip_nest_info { + u32 chip_id; + u64 pbase; + u64 vbase[IMC_NEST_MAX_PAGES]; + u64 size; +}; + +/* + * Place holder for nest pmu events and values. + */ +struct imc_events { + char *ev_name; + char *ev_value; +}; + +#define IMC_FORMAT_ATTR 0 +#define IMC_CPUMASK_ATTR 1 +#define IMC_EVENT_ATTR 2 +#define IMC_NULL_ATTR 3 + +/* + * Device tree parser code detects IMC pmu support and + * registers new IMC pmus. This structure will + * hold the pmu functions and attrs for each imc pmu and + * will be referenced at the time of pmu registration. + */ +struct imc_pmu { + struct pmu pmu; + int domain; + /* + * Attribute groups for the PMU. Slot 0 used for + * format attribute, slot 1 used for cpusmask attribute, + * slot 2 used for event attribute. Slot 3 keep as + * NULL. + */ + const struct attribute_group *attr_groups[4]; +}; + +/* + * Domains for IMC PMUs + */ +#define IMC_DOMAIN_NEST 1 +#define IMC_DOMAIN_UNKNOWN -1 + +#endif /* PPC_POWERNV_IMC_PMU_DEF_H */ -- 2.7.4