From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx0a-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3wRsX91xQXzDqhX for ; Tue, 16 May 2017 19:26:33 +1000 (AEST) Received: from pps.filterd (m0098417.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.20/8.16.0.20) with SMTP id v4G9NcXW021190 for ; Tue, 16 May 2017 05:26:30 -0400 Received: from e35.co.us.ibm.com (e35.co.us.ibm.com [32.97.110.153]) by mx0a-001b2d01.pphosted.com with ESMTP id 2aft10vdge-1 (version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT) for ; Tue, 16 May 2017 05:26:30 -0400 Received: from localhost by e35.co.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Tue, 16 May 2017 03:26:29 -0600 From: "Aneesh Kumar K.V" To: benh@kernel.crashing.org, paulus@samba.org, mpe@ellerman.id.au, Frederic Barrat Cc: linuxppc-dev@lists.ozlabs.org, "Aneesh Kumar K.V" Subject: [PATCH 1/3] powerpc: Add __hard_irqs_disabled() Date: Tue, 16 May 2017 14:56:20 +0530 Message-Id: <1494926782-25700-1-git-send-email-aneesh.kumar@linux.vnet.ibm.com> List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Add __hard_irqs_disabled() similar to arch_irqs_disabled to check whether irqs are hard disabled. Signed-off-by: Aneesh Kumar K.V --- arch/powerpc/include/asm/hw_irq.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/powerpc/include/asm/hw_irq.h b/arch/powerpc/include/asm/hw_irq.h index eba60416536e..541bd42f902f 100644 --- a/arch/powerpc/include/asm/hw_irq.h +++ b/arch/powerpc/include/asm/hw_irq.h @@ -88,6 +88,12 @@ static inline bool arch_irqs_disabled(void) return arch_irqs_disabled_flags(arch_local_save_flags()); } +static inline bool __hard_irqs_disabled(void) +{ + unsigned long flags = mfmsr(); + return (flags & MSR_EE) == 0; +} + #ifdef CONFIG_PPC_BOOK3E #define __hard_irq_enable() asm volatile("wrteei 1" : : : "memory") #define __hard_irq_disable() asm volatile("wrteei 0" : : : "memory") @@ -197,6 +203,7 @@ static inline bool arch_irqs_disabled(void) } #define hard_irq_disable() arch_local_irq_disable() +#define __hard_irqs_disabled() arch_irqs_disabled() static inline bool arch_irq_disabled_regs(struct pt_regs *regs) { -- 2.7.4