From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from leibniz.telenet-ops.be (leibniz.telenet-ops.be [IPv6:2a02:1800:110:4::f00:d]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3wfP9C15KtzDqMS for ; Fri, 2 Jun 2017 22:46:39 +1000 (AEST) Received: from baptiste.telenet-ops.be (baptiste.telenet-ops.be [IPv6:2a02:1800:120:4::f00:13]) by leibniz.telenet-ops.be (Postfix) with ESMTPS id 3wfP0Z01TlzMsf62 for ; Fri, 2 Jun 2017 14:39:10 +0200 (CEST) From: Geert Uytterhoeven To: David Airlie , Rob Herring , Mark Rutland , Carlo Caione , Kevin Hilman , Chanho Min , Catalin Marinas , Will Deacon Cc: Neil Armstrong , Benjamin Herrenschmidt , Paul Mackerras , Michael Ellerman , dri-devel@lists.freedesktop.org, linux-amlogic@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, Geert Uytterhoeven Subject: [PATCH v3 3/6] dt: booting-without-of: DT fix s/#interrupt-cell/#interrupt-cells/ Date: Fri, 2 Jun 2017 14:38:46 +0200 Message-Id: <1496407129-13527-4-git-send-email-geert+renesas@glider.be> In-Reply-To: <1496407129-13527-1-git-send-email-geert+renesas@glider.be> References: <1496407129-13527-1-git-send-email-geert+renesas@glider.be> List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Signed-off-by: Geert Uytterhoeven Acked-by: Rob Herring --- v3: - No changes, v2: - Add Acked-by. --- Documentation/devicetree/booting-without-of.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/booting-without-of.txt b/Documentation/devicetree/booting-without-of.txt index 280d283304bb82d8..f35d3adacb987f7d 100644 --- a/Documentation/devicetree/booting-without-of.txt +++ b/Documentation/devicetree/booting-without-of.txt @@ -1309,7 +1309,7 @@ number and level/sense information. All interrupt children in an OpenPIC interrupt domain use 2 cells per interrupt in their interrupts property. -The PCI bus binding specifies a #interrupt-cell value of 1 to encode +The PCI bus binding specifies a #interrupt-cells value of 1 to encode which interrupt pin (INTA,INTB,INTC,INTD) is used. 2) interrupt-parent property -- 2.7.4