From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx0a-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3wyX9W3h9qzDr4X for ; Thu, 29 Jun 2017 04:57:51 +1000 (AEST) Received: from pps.filterd (m0098420.ppops.net [127.0.0.1]) by mx0b-001b2d01.pphosted.com (8.16.0.20/8.16.0.20) with SMTP id v5SIsAgZ006294 for ; Wed, 28 Jun 2017 14:57:49 -0400 Received: from e23smtp03.au.ibm.com (e23smtp03.au.ibm.com [202.81.31.145]) by mx0b-001b2d01.pphosted.com with ESMTP id 2bccv0r9av-1 (version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT) for ; Wed, 28 Jun 2017 14:57:48 -0400 Received: from localhost by e23smtp03.au.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Thu, 29 Jun 2017 04:57:45 +1000 Received: from d23av02.au.ibm.com (d23av02.au.ibm.com [9.190.235.138]) by d23relay06.au.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id v5SIviIb4063706 for ; Thu, 29 Jun 2017 04:57:44 +1000 Received: from d23av02.au.ibm.com (localhost [127.0.0.1]) by d23av02.au.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id v5SIvZFb029704 for ; Thu, 29 Jun 2017 04:57:36 +1000 From: Anju T Sudhakar To: mpe@ellerman.id.au Cc: linux-kernel@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, ego@linux.vnet.ibm.com, bsingharora@gmail.com, anton@samba.org, sukadev@linux.vnet.ibm.com, mikey@neuling.org, stewart@linux.vnet.ibm.com, dja@axtens.net, eranian@google.com, hemant@linux.vnet.ibm.com, maddy@linux.vnet.ibm.com, anju@linux.vnet.ibm.com Subject: [PATCH v11 06/10] powerpc/powernv: Core IMC events detection Date: Thu, 29 Jun 2017 00:27:10 +0530 In-Reply-To: <1498676232-23841-1-git-send-email-anju@linux.vnet.ibm.com> References: <1498676232-23841-1-git-send-email-anju@linux.vnet.ibm.com> Message-Id: <1498676232-23841-6-git-send-email-anju@linux.vnet.ibm.com> List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , From: Madhavan Srinivasan This patch adds support for detection of core IMC events along with the Nest IMC events. It adds a new domain IMC_DOMAIN_CORE and its determined with the help of the "type" property in the IMC device tree. Signed-off-by: Anju T Sudhakar Signed-off-by: Hemant Kumar Signed-off-by: Madhavan Srinivasan --- arch/powerpc/include/asm/imc-pmu.h | 3 +++ arch/powerpc/perf/imc-pmu.c | 2 ++ arch/powerpc/platforms/powernv/opal-imc.c | 14 +++++++++++--- 3 files changed, 16 insertions(+), 3 deletions(-) diff --git a/arch/powerpc/include/asm/imc-pmu.h b/arch/powerpc/include/asm/imc-pmu.h index 650c1e8..e9da151 100644 --- a/arch/powerpc/include/asm/imc-pmu.h +++ b/arch/powerpc/include/asm/imc-pmu.h @@ -97,6 +97,7 @@ struct imc_pmu { /* In-Memory Collection Counters Type */ enum { + IMC_COUNTER_PER_CORE = 0x4, IMC_COUNTER_PER_CHIP = 0x10, }; @@ -104,7 +105,9 @@ enum { * Domains for IMC PMUs */ #define IMC_DOMAIN_NEST 1 +#define IMC_DOMAIN_CORE 2 extern struct imc_pmu *per_nest_pmu_arr[IMC_MAX_PMUS]; +extern struct imc_pmu *core_imc_pmu; extern int init_imc_pmu(struct imc_events *events, int idx, struct imc_pmu *pmu_ptr); #endif /* PPC_POWERNV_IMC_PMU_DEF_H */ diff --git a/arch/powerpc/perf/imc-pmu.c b/arch/powerpc/perf/imc-pmu.c index b0bcb77..f4856eb 100644 --- a/arch/powerpc/perf/imc-pmu.c +++ b/arch/powerpc/perf/imc-pmu.c @@ -31,6 +31,8 @@ static DEFINE_MUTEX(imc_nest_inited_reserve); static DEFINE_MUTEX(imc_nest_reserve); +struct imc_pmu *core_imc_pmu; + struct imc_pmu *imc_event_to_pmu(struct perf_event *event) { return container_of(event->pmu, struct imc_pmu, pmu); diff --git a/arch/powerpc/platforms/powernv/opal-imc.c b/arch/powerpc/platforms/powernv/opal-imc.c index a970ed3..98e7b0f5 100644 --- a/arch/powerpc/platforms/powernv/opal-imc.c +++ b/arch/powerpc/platforms/powernv/opal-imc.c @@ -379,7 +379,7 @@ static int imc_get_mem_addr_nest(struct device_node *node, /* * imc_pmu_create : Takes the parent device which is the pmu unit, pmu_index * and domain as the inputs. - * Allocates memory for the pmu, sets up its domain (NEST), and + * Allocates memory for the pmu, sets up its domain (NEST/CORE), and * calls imc_events_setup() to allocate memory for the events supported * by this pmu. Assigns a name for the pmu. * @@ -406,7 +406,10 @@ static int imc_pmu_create(struct device_node *parent, int pmu_index, int domain) pmu_ptr->domain = domain; /* Needed for hotplug/migration */ - per_nest_pmu_arr[pmu_index] = pmu_ptr; + if (pmu_ptr->domain == IMC_DOMAIN_CORE) + core_imc_pmu = pmu_ptr; + else if (pmu_ptr->domain == IMC_DOMAIN_NEST) + per_nest_pmu_arr[pmu_index] = pmu_ptr; pp = of_find_property(parent, "name", NULL); if (!pp) { @@ -427,7 +430,10 @@ static int imc_pmu_create(struct device_node *parent, int pmu_index, int domain) goto free_pmu; } /* Save the name to register it later */ - sprintf(buf, "nest_%s", (char *)pp->value); + if (pmu_ptr->domain == IMC_DOMAIN_NEST) + sprintf(buf, "nest_%s", (char *)pp->value); + else + sprintf(buf, "%s_imc", (char *)pp->value); pmu_ptr->pmu.name = (char *)buf; if (of_property_read_u32(parent, "size", &pmu_ptr->counter_mem_size)) @@ -504,6 +510,8 @@ static int opal_imc_counters_probe(struct platform_device *pdev) continue; if (type == IMC_COUNTER_PER_CHIP) domain = IMC_DOMAIN_NEST; + else if (type == IMC_COUNTER_PER_CORE) + domain = IMC_DOMAIN_CORE; else continue; if (!imc_pmu_create(imc_dev, pmu_count, domain)) -- 2.7.4