* [PATCH v10 1/4] irqchip/qeic: move qeic driver from drivers/soc/fsl/qe
2017-08-07 3:07 [PATCH v10 0/4] this patchset is to remove PPCisms for QEIC Zhao Qiang
@ 2017-08-07 3:07 ` Zhao Qiang
2017-08-07 3:07 ` [PATCH v10 2/4] irqchip/qeic: merge qeic init code from platforms to a common function Zhao Qiang
` (3 subsequent siblings)
4 siblings, 0 replies; 16+ messages in thread
From: Zhao Qiang @ 2017-08-07 3:07 UTC (permalink / raw)
To: tglx; +Cc: oss, xiaobo.xie, linux-kernel, linuxppc-dev, Zhao Qiang
move the driver from drivers/soc/fsl/qe to drivers/irqchip,
merge qe_ic.h and qe_ic.c into irq-qeic.c.
Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
---
MAINTAINERS | 6 ++
drivers/irqchip/Makefile | 1 +
drivers/{soc/fsl/qe/qe_ic.c => irqchip/irq-qeic.c} | 95 ++++++++++++++++++-
drivers/soc/fsl/qe/Makefile | 2 +-
drivers/soc/fsl/qe/qe_ic.h | 103 ---------------------
5 files changed, 100 insertions(+), 107 deletions(-)
rename drivers/{soc/fsl/qe/qe_ic.c => irqchip/irq-qeic.c} (85%)
delete mode 100644 drivers/soc/fsl/qe/qe_ic.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 567343b..1288329 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -5462,6 +5462,12 @@ F: drivers/soc/fsl/qe/
F: include/soc/fsl/*qe*.h
F: include/soc/fsl/*ucc*.h
+FREESCALE QEIC DRIVERS
+M: Qiang Zhao <qiang.zhao@nxp.com>
+L: linux-kernel@vger.kernel.org
+S: Maintained
+F: drivers/irqchip/irq-qeic.c
+
FREESCALE QUICC ENGINE UCC ETHERNET DRIVER
M: Li Yang <leoyang.li@nxp.com>
L: netdev@vger.kernel.org
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index e88d856..b8eae87 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -78,3 +78,4 @@ obj-$(CONFIG_EZNPS_GIC) += irq-eznps.o
obj-$(CONFIG_ARCH_ASPEED) += irq-aspeed-vic.o irq-aspeed-i2c-ic.o
obj-$(CONFIG_STM32_EXTI) += irq-stm32-exti.o
obj-$(CONFIG_QCOM_IRQ_COMBINER) += qcom-irq-combiner.o
+obj-$(CONFIG_QUICC_ENGINE) += irq-qeic.o
diff --git a/drivers/soc/fsl/qe/qe_ic.c b/drivers/irqchip/irq-qeic.c
similarity index 85%
rename from drivers/soc/fsl/qe/qe_ic.c
rename to drivers/irqchip/irq-qeic.c
index ec2ca86..9b4660c 100644
--- a/drivers/soc/fsl/qe/qe_ic.c
+++ b/drivers/irqchip/irq-qeic.c
@@ -1,7 +1,7 @@
/*
- * arch/powerpc/sysdev/qe_lib/qe_ic.c
+ * drivers/irqchip/irq-qeic.c
*
- * Copyright (C) 2006 Freescale Semiconductor, Inc. All rights reserved.
+ * Copyright (C) 2016 Freescale Semiconductor, Inc. All rights reserved.
*
* Author: Li Yang <leoli@freescale.com>
* Based on code from Shlomi Gridish <gridish@freescale.com>
@@ -30,7 +30,96 @@
#include <asm/io.h>
#include <soc/fsl/qe/qe_ic.h>
-#include "qe_ic.h"
+#define NR_QE_IC_INTS 64
+
+/* QE IC registers offset */
+#define QEIC_CICR 0x00
+#define QEIC_CIVEC 0x04
+#define QEIC_CRIPNR 0x08
+#define QEIC_CIPNR 0x0c
+#define QEIC_CIPXCC 0x10
+#define QEIC_CIPYCC 0x14
+#define QEIC_CIPWCC 0x18
+#define QEIC_CIPZCC 0x1c
+#define QEIC_CIMR 0x20
+#define QEIC_CRIMR 0x24
+#define QEIC_CICNR 0x28
+#define QEIC_CIPRTA 0x30
+#define QEIC_CIPRTB 0x34
+#define QEIC_CRICR 0x3c
+#define QEIC_CHIVEC 0x60
+
+/* Interrupt priority registers */
+#define CIPCC_SHIFT_PRI0 29
+#define CIPCC_SHIFT_PRI1 26
+#define CIPCC_SHIFT_PRI2 23
+#define CIPCC_SHIFT_PRI3 20
+#define CIPCC_SHIFT_PRI4 13
+#define CIPCC_SHIFT_PRI5 10
+#define CIPCC_SHIFT_PRI6 7
+#define CIPCC_SHIFT_PRI7 4
+
+/* CICR priority modes */
+#define CICR_GWCC 0x00040000
+#define CICR_GXCC 0x00020000
+#define CICR_GYCC 0x00010000
+#define CICR_GZCC 0x00080000
+#define CICR_GRTA 0x00200000
+#define CICR_GRTB 0x00400000
+#define CICR_HPIT_SHIFT 8
+#define CICR_HPIT_MASK 0x00000300
+#define CICR_HP_SHIFT 24
+#define CICR_HP_MASK 0x3f000000
+
+/* CICNR */
+#define CICNR_WCC1T_SHIFT 20
+#define CICNR_ZCC1T_SHIFT 28
+#define CICNR_YCC1T_SHIFT 12
+#define CICNR_XCC1T_SHIFT 4
+
+/* CRICR */
+#define CRICR_RTA1T_SHIFT 20
+#define CRICR_RTB1T_SHIFT 28
+
+/* Signal indicator */
+#define SIGNAL_MASK 3
+#define SIGNAL_HIGH 2
+#define SIGNAL_LOW 0
+
+struct qe_ic {
+ /* Control registers offset */
+ u32 __iomem *regs;
+
+ /* The remapper for this QEIC */
+ struct irq_domain *irqhost;
+
+ /* The "linux" controller struct */
+ struct irq_chip hc_irq;
+
+ /* VIRQ numbers of QE high/low irqs */
+ unsigned int virq_high;
+ unsigned int virq_low;
+};
+
+/*
+ * QE interrupt controller internal structure
+ */
+struct qe_ic_info {
+ /* location of this source at the QIMR register. */
+ u32 mask;
+
+ /* Mask register offset */
+ u32 mask_reg;
+
+ /*
+ * for grouped interrupts sources - the interrupt
+ * code as appears at the group priority register
+ */
+ u8 pri_code;
+
+ /* Group priority register offset */
+ u32 pri_reg;
+};
static DEFINE_RAW_SPINLOCK(qe_ic_lock);
diff --git a/drivers/soc/fsl/qe/Makefile b/drivers/soc/fsl/qe/Makefile
index 2031d38..51e4726 100644
--- a/drivers/soc/fsl/qe/Makefile
+++ b/drivers/soc/fsl/qe/Makefile
@@ -1,7 +1,7 @@
#
# Makefile for the linux ppc-specific parts of QE
#
-obj-$(CONFIG_QUICC_ENGINE)+= qe.o qe_common.o qe_ic.o qe_io.o
+obj-$(CONFIG_QUICC_ENGINE)+= qe.o qe_common.o qe_io.o
obj-$(CONFIG_CPM) += qe_common.o
obj-$(CONFIG_UCC) += ucc.o
obj-$(CONFIG_UCC_SLOW) += ucc_slow.o
diff --git a/drivers/soc/fsl/qe/qe_ic.h b/drivers/soc/fsl/qe/qe_ic.h
deleted file mode 100644
index 926a2ed..0000000
--- a/drivers/soc/fsl/qe/qe_ic.h
+++ /dev/null
@@ -1,103 +0,0 @@
-/*
- * drivers/soc/fsl/qe/qe_ic.h
- *
- * QUICC ENGINE Interrupt Controller Header
- *
- * Copyright (C) 2006 Freescale Semiconductor, Inc. All rights reserved.
- *
- * Author: Li Yang <leoli@freescale.com>
- * Based on code from Shlomi Gridish <gridish@freescale.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- */
-#ifndef _POWERPC_SYSDEV_QE_IC_H
-#define _POWERPC_SYSDEV_QE_IC_H
-
-#include <soc/fsl/qe/qe_ic.h>
-
-#define NR_QE_IC_INTS 64
-
-/* QE IC registers offset */
-#define QEIC_CICR 0x00
-#define QEIC_CIVEC 0x04
-#define QEIC_CRIPNR 0x08
-#define QEIC_CIPNR 0x0c
-#define QEIC_CIPXCC 0x10
-#define QEIC_CIPYCC 0x14
-#define QEIC_CIPWCC 0x18
-#define QEIC_CIPZCC 0x1c
-#define QEIC_CIMR 0x20
-#define QEIC_CRIMR 0x24
-#define QEIC_CICNR 0x28
-#define QEIC_CIPRTA 0x30
-#define QEIC_CIPRTB 0x34
-#define QEIC_CRICR 0x3c
-#define QEIC_CHIVEC 0x60
-
-/* Interrupt priority registers */
-#define CIPCC_SHIFT_PRI0 29
-#define CIPCC_SHIFT_PRI1 26
-#define CIPCC_SHIFT_PRI2 23
-#define CIPCC_SHIFT_PRI3 20
-#define CIPCC_SHIFT_PRI4 13
-#define CIPCC_SHIFT_PRI5 10
-#define CIPCC_SHIFT_PRI6 7
-#define CIPCC_SHIFT_PRI7 4
-
-/* CICR priority modes */
-#define CICR_GWCC 0x00040000
-#define CICR_GXCC 0x00020000
-#define CICR_GYCC 0x00010000
-#define CICR_GZCC 0x00080000
-#define CICR_GRTA 0x00200000
-#define CICR_GRTB 0x00400000
-#define CICR_HPIT_SHIFT 8
-#define CICR_HPIT_MASK 0x00000300
-#define CICR_HP_SHIFT 24
-#define CICR_HP_MASK 0x3f000000
-
-/* CICNR */
-#define CICNR_WCC1T_SHIFT 20
-#define CICNR_ZCC1T_SHIFT 28
-#define CICNR_YCC1T_SHIFT 12
-#define CICNR_XCC1T_SHIFT 4
-
-/* CRICR */
-#define CRICR_RTA1T_SHIFT 20
-#define CRICR_RTB1T_SHIFT 28
-
-/* Signal indicator */
-#define SIGNAL_MASK 3
-#define SIGNAL_HIGH 2
-#define SIGNAL_LOW 0
-
-struct qe_ic {
- /* Control registers offset */
- volatile u32 __iomem *regs;
-
- /* The remapper for this QEIC */
- struct irq_domain *irqhost;
-
- /* The "linux" controller struct */
- struct irq_chip hc_irq;
-
- /* VIRQ numbers of QE high/low irqs */
- unsigned int virq_high;
- unsigned int virq_low;
-};
-
-/*
- * QE interrupt controller internal structure
- */
-struct qe_ic_info {
- u32 mask; /* location of this source at the QIMR register. */
- u32 mask_reg; /* Mask register offset */
- u8 pri_code; /* for grouped interrupts sources - the interrupt
- code as appears at the group priority register */
- u32 pri_reg; /* Group priority register offset */
-};
-
-#endif /* _POWERPC_SYSDEV_QE_IC_H */
--
2.1.0.27.g96db324
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH v10 2/4] irqchip/qeic: merge qeic init code from platforms to a common function
2017-08-07 3:07 [PATCH v10 0/4] this patchset is to remove PPCisms for QEIC Zhao Qiang
2017-08-07 3:07 ` [PATCH v10 1/4] irqchip/qeic: move qeic driver from drivers/soc/fsl/qe Zhao Qiang
@ 2017-08-07 3:07 ` Zhao Qiang
2017-08-07 3:07 ` [PATCH v10 3/4] irqchip/qeic: merge qeic_of_init into qe_ic_init Zhao Qiang
` (2 subsequent siblings)
4 siblings, 0 replies; 16+ messages in thread
From: Zhao Qiang @ 2017-08-07 3:07 UTC (permalink / raw)
To: tglx; +Cc: oss, xiaobo.xie, linux-kernel, linuxppc-dev, Zhao Qiang
The codes of qe_ic init from a variety of platforms are redundant,
merge them to a common function and put it to irqchip/irq-qeic.c
For non-p1021_mds mpc85xx_mds boards, use "qe_ic_init(np, 0,
qe_ic_cascade_low_mpic, qe_ic_cascade_high_mpic);" instead of
"qe_ic_init(np, 0, qe_ic_cascade_muxed_mpic, NULL);".
qe_ic_cascade_muxed_mpic was used for boards has the same interrupt
number for low interrupt and high interrupt, qe_ic_init has checked
if "low interrupt == high interrupt"
Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
---
arch/powerpc/platforms/83xx/misc.c | 15 ---------------
arch/powerpc/platforms/85xx/corenet_generic.c | 9 ---------
arch/powerpc/platforms/85xx/mpc85xx_mds.c | 14 --------------
arch/powerpc/platforms/85xx/mpc85xx_rdb.c | 16 ----------------
arch/powerpc/platforms/85xx/twr_p102x.c | 14 --------------
drivers/irqchip/irq-qeic.c | 13 +++++++++++++
6 files changed, 13 insertions(+), 68 deletions(-)
diff --git a/arch/powerpc/platforms/83xx/misc.c b/arch/powerpc/platforms/83xx/misc.c
index d75c981..c09a135 100644
--- a/arch/powerpc/platforms/83xx/misc.c
+++ b/arch/powerpc/platforms/83xx/misc.c
@@ -93,24 +93,9 @@ void __init mpc83xx_ipic_init_IRQ(void)
}
#ifdef CONFIG_QUICC_ENGINE
-void __init mpc83xx_qe_init_IRQ(void)
-{
- struct device_node *np;
-
- np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
- if (!np) {
- np = of_find_node_by_type(NULL, "qeic");
- if (!np)
- return;
- }
- qe_ic_init(np, 0, qe_ic_cascade_low_ipic, qe_ic_cascade_high_ipic);
- of_node_put(np);
-}
-
void __init mpc83xx_ipic_and_qe_init_IRQ(void)
{
mpc83xx_ipic_init_IRQ();
- mpc83xx_qe_init_IRQ();
}
#endif /* CONFIG_QUICC_ENGINE */
diff --git a/arch/powerpc/platforms/85xx/corenet_generic.c b/arch/powerpc/platforms/85xx/corenet_generic.c
index ac191a7..1b385ac 100644
--- a/arch/powerpc/platforms/85xx/corenet_generic.c
+++ b/arch/powerpc/platforms/85xx/corenet_generic.c
@@ -41,8 +41,6 @@ void __init corenet_gen_pic_init(void)
unsigned int flags = MPIC_BIG_ENDIAN | MPIC_SINGLE_DEST_CPU |
MPIC_NO_RESET;
- struct device_node *np;
-
if (ppc_md.get_irq == mpic_get_coreint_irq)
flags |= MPIC_ENABLE_COREINT;
@@ -50,13 +48,6 @@ void __init corenet_gen_pic_init(void)
BUG_ON(mpic == NULL);
mpic_init(mpic);
-
- np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
- if (np) {
- qe_ic_init(np, 0, qe_ic_cascade_low_mpic,
- qe_ic_cascade_high_mpic);
- of_node_put(np);
- }
}
/*
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_mds.c b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
index d7e440e..06f34a9 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_mds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
@@ -283,20 +283,6 @@ static void __init mpc85xx_mds_qeic_init(void)
of_node_put(np);
return;
}
-
- np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
- if (!np) {
- np = of_find_node_by_type(NULL, "qeic");
- if (!np)
- return;
- }
-
- if (machine_is(p1021_mds))
- qe_ic_init(np, 0, qe_ic_cascade_low_mpic,
- qe_ic_cascade_high_mpic);
- else
- qe_ic_init(np, 0, qe_ic_cascade_muxed_mpic, NULL);
- of_node_put(np);
}
#else
static void __init mpc85xx_mds_qe_init(void) { }
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
index 1006950..000d385 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
@@ -48,10 +48,6 @@ void __init mpc85xx_rdb_pic_init(void)
{
struct mpic *mpic;
-#ifdef CONFIG_QUICC_ENGINE
- struct device_node *np;
-#endif
-
if (of_machine_is_compatible("fsl,MPC85XXRDB-CAMP")) {
mpic = mpic_alloc(NULL, 0, MPIC_NO_RESET |
MPIC_BIG_ENDIAN |
@@ -66,18 +62,6 @@ void __init mpc85xx_rdb_pic_init(void)
BUG_ON(mpic == NULL);
mpic_init(mpic);
-
-#ifdef CONFIG_QUICC_ENGINE
- np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
- if (np) {
- qe_ic_init(np, 0, qe_ic_cascade_low_mpic,
- qe_ic_cascade_high_mpic);
- of_node_put(np);
-
- } else
- pr_err("%s: Could not find qe-ic node\n", __func__);
-#endif
-
}
/*
diff --git a/arch/powerpc/platforms/85xx/twr_p102x.c b/arch/powerpc/platforms/85xx/twr_p102x.c
index 360f625..6be9b33 100644
--- a/arch/powerpc/platforms/85xx/twr_p102x.c
+++ b/arch/powerpc/platforms/85xx/twr_p102x.c
@@ -35,26 +35,12 @@ static void __init twr_p1025_pic_init(void)
{
struct mpic *mpic;
-#ifdef CONFIG_QUICC_ENGINE
- struct device_node *np;
-#endif
-
mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN |
MPIC_SINGLE_DEST_CPU,
0, 256, " OpenPIC ");
BUG_ON(mpic == NULL);
mpic_init(mpic);
-
-#ifdef CONFIG_QUICC_ENGINE
- np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
- if (np) {
- qe_ic_init(np, 0, qe_ic_cascade_low_mpic,
- qe_ic_cascade_high_mpic);
- of_node_put(np);
- } else
- pr_err("Could not find qe-ic node\n");
-#endif
}
/* ************************************************************************
diff --git a/drivers/irqchip/irq-qeic.c b/drivers/irqchip/irq-qeic.c
index 9b4660c..8287c22 100644
--- a/drivers/irqchip/irq-qeic.c
+++ b/drivers/irqchip/irq-qeic.c
@@ -18,6 +18,7 @@
#include <linux/of_address.h>
#include <linux/kernel.h>
#include <linux/init.h>
+#include <linux/irqchip.h>
#include <linux/errno.h>
#include <linux/reboot.h>
#include <linux/slab.h>
@@ -598,4 +599,16 @@ static int __init init_qe_ic_sysfs(void)
return 0;
}
+static int __init qeic_of_init(struct device_node *node,
+ struct device_node *parent)
+{
+ if (!node)
+ return -ENODEV;
+ qe_ic_init(node, 0, qe_ic_cascade_low_mpic,
+ qe_ic_cascade_high_mpic);
+ of_node_put(node);
+ return 0;
+}
+
+IRQCHIP_DECLARE(qeic, "fsl,qe-ic", qeic_of_init);
subsys_initcall(init_qe_ic_sysfs);
--
2.1.0.27.g96db324
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH v10 3/4] irqchip/qeic: merge qeic_of_init into qe_ic_init
2017-08-07 3:07 [PATCH v10 0/4] this patchset is to remove PPCisms for QEIC Zhao Qiang
2017-08-07 3:07 ` [PATCH v10 1/4] irqchip/qeic: move qeic driver from drivers/soc/fsl/qe Zhao Qiang
2017-08-07 3:07 ` [PATCH v10 2/4] irqchip/qeic: merge qeic init code from platforms to a common function Zhao Qiang
@ 2017-08-07 3:07 ` Zhao Qiang
2017-08-07 3:07 ` [PATCH v10 4/4] irqchip/qeic: remove PPCisms for QEIC Zhao Qiang
2017-10-24 1:51 ` [PATCH v10 0/4] this patchset is to " Qiang Zhao
4 siblings, 0 replies; 16+ messages in thread
From: Zhao Qiang @ 2017-08-07 3:07 UTC (permalink / raw)
To: tglx; +Cc: oss, xiaobo.xie, linux-kernel, linuxppc-dev, Zhao Qiang
qeic_of_init just get device_node of qeic from dtb and call qe_ic_init,
pass the device_node to qe_ic_init.
So merge qeic_of_init into qe_ic_init to get the qeic node in
qe_ic_init.
Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
---
drivers/irqchip/irq-qeic.c | 90 ++++++++++++++++++++--------------------------
include/soc/fsl/qe/qe_ic.h | 7 ----
2 files changed, 39 insertions(+), 58 deletions(-)
diff --git a/drivers/irqchip/irq-qeic.c b/drivers/irqchip/irq-qeic.c
index 8287c22..a2d8084 100644
--- a/drivers/irqchip/irq-qeic.c
+++ b/drivers/irqchip/irq-qeic.c
@@ -407,27 +407,33 @@ unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic)
return irq_linear_revmap(qe_ic->irqhost, irq);
}
-void __init qe_ic_init(struct device_node *node, unsigned int flags,
- void (*low_handler)(struct irq_desc *desc),
- void (*high_handler)(struct irq_desc *desc))
+static int __init qe_ic_init(struct device_node *node, unsigned int flags)
{
struct qe_ic *qe_ic;
struct resource res;
- u32 temp = 0, ret, high_active = 0;
+ u32 temp = 0, high_active = 0;
+ int ret = 0;
+
+ if (!node)
+ return -ENODEV;
ret = of_address_to_resource(node, 0, &res);
- if (ret)
- return;
+ if (ret) {
+ ret = -ENODEV;
+ goto err_put_node;
+ }
qe_ic = kzalloc(sizeof(*qe_ic), GFP_KERNEL);
- if (qe_ic == NULL)
- return;
+ if (qe_ic == NULL) {
+ ret = -ENOMEM;
+ goto err_put_node;
+ }
qe_ic->irqhost = irq_domain_add_linear(node, NR_QE_IC_INTS,
&qe_ic_host_ops, qe_ic);
if (qe_ic->irqhost == NULL) {
- kfree(qe_ic);
- return;
+ ret = -ENOMEM;
+ goto err_free_qe_ic;
}
qe_ic->regs = ioremap(res.start, resource_size(&res));
@@ -438,9 +444,9 @@ void __init qe_ic_init(struct device_node *node, unsigned int flags,
qe_ic->virq_low = irq_of_parse_and_map(node, 1);
if (qe_ic->virq_low == NO_IRQ) {
- printk(KERN_ERR "Failed to map QE_IC low IRQ\n");
- kfree(qe_ic);
- return;
+ pr_err("Failed to map QE_IC low IRQ\n");
+ ret = -ENOMEM;
+ goto err_domain_remove;
}
/* default priority scheme is grouped. If spread mode is */
@@ -467,13 +473,24 @@ void __init qe_ic_init(struct device_node *node, unsigned int flags,
qe_ic_write(qe_ic->regs, QEIC_CICR, temp);
irq_set_handler_data(qe_ic->virq_low, qe_ic);
- irq_set_chained_handler(qe_ic->virq_low, low_handler);
+ irq_set_chained_handler(qe_ic->virq_low, qe_ic_cascade_low_mpic);
if (qe_ic->virq_high != NO_IRQ &&
qe_ic->virq_high != qe_ic->virq_low) {
irq_set_handler_data(qe_ic->virq_high, qe_ic);
- irq_set_chained_handler(qe_ic->virq_high, high_handler);
+ irq_set_chained_handler(qe_ic->virq_high,
+ qe_ic_cascade_high_mpic);
}
+ of_node_put(node);
+ return 0;
+
+err_domain_remove:
+ irq_domain_remove(qe_ic->irqhost);
+err_free_qe_ic:
+ kfree(qe_ic);
+err_put_node:
+ of_node_put(node);
+ return ret;
}
void qe_ic_set_highest_priority(unsigned int virq, int high)
@@ -570,45 +587,16 @@ int qe_ic_set_high_priority(unsigned int virq, unsigned int priority, int high)
return 0;
}
-static struct bus_type qe_ic_subsys = {
- .name = "qe_ic",
- .dev_name = "qe_ic",
-};
-
-static struct device device_qe_ic = {
- .id = 0,
- .bus = &qe_ic_subsys,
-};
-
-static int __init init_qe_ic_sysfs(void)
+static int __init init_qe_ic(struct device_node *node,
+ struct device_node *parent)
{
- int rc;
-
- printk(KERN_DEBUG "Registering qe_ic with sysfs...\n");
+ int ret;
- rc = subsys_system_register(&qe_ic_subsys, NULL);
- if (rc) {
- printk(KERN_ERR "Failed registering qe_ic sys class\n");
- return -ENODEV;
- }
- rc = device_register(&device_qe_ic);
- if (rc) {
- printk(KERN_ERR "Failed registering qe_ic sys device\n");
- return -ENODEV;
- }
- return 0;
-}
+ ret = qe_ic_init(node, 0);
+ if (ret)
+ return ret;
-static int __init qeic_of_init(struct device_node *node,
- struct device_node *parent)
-{
- if (!node)
- return -ENODEV;
- qe_ic_init(node, 0, qe_ic_cascade_low_mpic,
- qe_ic_cascade_high_mpic);
- of_node_put(node);
return 0;
}
-IRQCHIP_DECLARE(qeic, "fsl,qe-ic", qeic_of_init);
-subsys_initcall(init_qe_ic_sysfs);
+IRQCHIP_DECLARE(qeic, "fsl,qe-ic", init_qe_ic);
diff --git a/include/soc/fsl/qe/qe_ic.h b/include/soc/fsl/qe/qe_ic.h
index 1e155ca..6113699 100644
--- a/include/soc/fsl/qe/qe_ic.h
+++ b/include/soc/fsl/qe/qe_ic.h
@@ -58,16 +58,9 @@ enum qe_ic_grp_id {
};
#ifdef CONFIG_QUICC_ENGINE
-void qe_ic_init(struct device_node *node, unsigned int flags,
- void (*low_handler)(struct irq_desc *desc),
- void (*high_handler)(struct irq_desc *desc));
unsigned int qe_ic_get_low_irq(struct qe_ic *qe_ic);
unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic);
#else
-static inline void qe_ic_init(struct device_node *node, unsigned int flags,
- void (*low_handler)(struct irq_desc *desc),
- void (*high_handler)(struct irq_desc *desc))
-{}
static inline unsigned int qe_ic_get_low_irq(struct qe_ic *qe_ic)
{ return 0; }
static inline unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic)
--
2.1.0.27.g96db324
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH v10 4/4] irqchip/qeic: remove PPCisms for QEIC
2017-08-07 3:07 [PATCH v10 0/4] this patchset is to remove PPCisms for QEIC Zhao Qiang
` (2 preceding siblings ...)
2017-08-07 3:07 ` [PATCH v10 3/4] irqchip/qeic: merge qeic_of_init into qe_ic_init Zhao Qiang
@ 2017-08-07 3:07 ` Zhao Qiang
2017-08-07 7:02 ` Michael Ellerman
2017-10-24 1:51 ` [PATCH v10 0/4] this patchset is to " Qiang Zhao
4 siblings, 1 reply; 16+ messages in thread
From: Zhao Qiang @ 2017-08-07 3:07 UTC (permalink / raw)
To: tglx; +Cc: oss, xiaobo.xie, linux-kernel, linuxppc-dev, Zhao Qiang
QEIC was supported on PowerPC, and dependent on PPC,
Now it is supported on other platforms, so remove PPCisms.
Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
---
arch/powerpc/platforms/83xx/km83xx.c | 1 -
arch/powerpc/platforms/83xx/misc.c | 1 -
arch/powerpc/platforms/83xx/mpc832x_mds.c | 1 -
arch/powerpc/platforms/83xx/mpc832x_rdb.c | 1 -
arch/powerpc/platforms/83xx/mpc836x_mds.c | 1 -
arch/powerpc/platforms/83xx/mpc836x_rdk.c | 1 -
arch/powerpc/platforms/85xx/corenet_generic.c | 1 -
arch/powerpc/platforms/85xx/mpc85xx_mds.c | 1 -
arch/powerpc/platforms/85xx/mpc85xx_rdb.c | 1 -
arch/powerpc/platforms/85xx/twr_p102x.c | 1 -
drivers/irqchip/irq-qeic.c | 188 +++++++++++---------------
include/soc/fsl/qe/qe_ic.h | 132 ------------------
12 files changed, 80 insertions(+), 250 deletions(-)
delete mode 100644 include/soc/fsl/qe/qe_ic.h
diff --git a/arch/powerpc/platforms/83xx/km83xx.c b/arch/powerpc/platforms/83xx/km83xx.c
index d8642a4..b1cef0a 100644
--- a/arch/powerpc/platforms/83xx/km83xx.c
+++ b/arch/powerpc/platforms/83xx/km83xx.c
@@ -38,7 +38,6 @@
#include <sysdev/fsl_soc.h>
#include <sysdev/fsl_pci.h>
#include <soc/fsl/qe/qe.h>
-#include <soc/fsl/qe/qe_ic.h>
#include "mpc83xx.h"
diff --git a/arch/powerpc/platforms/83xx/misc.c b/arch/powerpc/platforms/83xx/misc.c
index c09a135..07a0e61 100644
--- a/arch/powerpc/platforms/83xx/misc.c
+++ b/arch/powerpc/platforms/83xx/misc.c
@@ -17,7 +17,6 @@
#include <asm/io.h>
#include <asm/hw_irq.h>
#include <asm/ipic.h>
-#include <soc/fsl/qe/qe_ic.h>
#include <sysdev/fsl_soc.h>
#include <sysdev/fsl_pci.h>
diff --git a/arch/powerpc/platforms/83xx/mpc832x_mds.c b/arch/powerpc/platforms/83xx/mpc832x_mds.c
index bb7b25a..a1cadf4 100644
--- a/arch/powerpc/platforms/83xx/mpc832x_mds.c
+++ b/arch/powerpc/platforms/83xx/mpc832x_mds.c
@@ -37,7 +37,6 @@
#include <sysdev/fsl_soc.h>
#include <sysdev/fsl_pci.h>
#include <soc/fsl/qe/qe.h>
-#include <soc/fsl/qe/qe_ic.h>
#include "mpc83xx.h"
diff --git a/arch/powerpc/platforms/83xx/mpc832x_rdb.c b/arch/powerpc/platforms/83xx/mpc832x_rdb.c
index d7c9b18..6c66527 100644
--- a/arch/powerpc/platforms/83xx/mpc832x_rdb.c
+++ b/arch/powerpc/platforms/83xx/mpc832x_rdb.c
@@ -26,7 +26,6 @@
#include <asm/ipic.h>
#include <asm/udbg.h>
#include <soc/fsl/qe/qe.h>
-#include <soc/fsl/qe/qe_ic.h>
#include <sysdev/fsl_soc.h>
#include <sysdev/fsl_pci.h>
diff --git a/arch/powerpc/platforms/83xx/mpc836x_mds.c b/arch/powerpc/platforms/83xx/mpc836x_mds.c
index 4fc3051..9234d63 100644
--- a/arch/powerpc/platforms/83xx/mpc836x_mds.c
+++ b/arch/powerpc/platforms/83xx/mpc836x_mds.c
@@ -45,7 +45,6 @@
#include <sysdev/fsl_pci.h>
#include <sysdev/simple_gpio.h>
#include <soc/fsl/qe/qe.h>
-#include <soc/fsl/qe/qe_ic.h>
#include "mpc83xx.h"
diff --git a/arch/powerpc/platforms/83xx/mpc836x_rdk.c b/arch/powerpc/platforms/83xx/mpc836x_rdk.c
index 93f024f..82fa344 100644
--- a/arch/powerpc/platforms/83xx/mpc836x_rdk.c
+++ b/arch/powerpc/platforms/83xx/mpc836x_rdk.c
@@ -21,7 +21,6 @@
#include <asm/ipic.h>
#include <asm/udbg.h>
#include <soc/fsl/qe/qe.h>
-#include <soc/fsl/qe/qe_ic.h>
#include <sysdev/fsl_soc.h>
#include <sysdev/fsl_pci.h>
diff --git a/arch/powerpc/platforms/85xx/corenet_generic.c b/arch/powerpc/platforms/85xx/corenet_generic.c
index 1b385ac..9ca27b1 100644
--- a/arch/powerpc/platforms/85xx/corenet_generic.c
+++ b/arch/powerpc/platforms/85xx/corenet_generic.c
@@ -27,7 +27,6 @@
#include <asm/udbg.h>
#include <asm/mpic.h>
#include <asm/ehv_pic.h>
-#include <soc/fsl/qe/qe_ic.h>
#include <linux/of_platform.h>
#include <sysdev/fsl_soc.h>
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_mds.c b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
index 06f34a9..8102e5f 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_mds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
@@ -49,7 +49,6 @@
#include <sysdev/fsl_pci.h>
#include <sysdev/simple_gpio.h>
#include <soc/fsl/qe/qe.h>
-#include <soc/fsl/qe/qe_ic.h>
#include <asm/mpic.h>
#include <asm/swiotlb.h>
#include "smp.h"
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
index 000d385..f806b6b 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
@@ -27,7 +27,6 @@
#include <asm/udbg.h>
#include <asm/mpic.h>
#include <soc/fsl/qe/qe.h>
-#include <soc/fsl/qe/qe_ic.h>
#include <sysdev/fsl_soc.h>
#include <sysdev/fsl_pci.h>
diff --git a/arch/powerpc/platforms/85xx/twr_p102x.c b/arch/powerpc/platforms/85xx/twr_p102x.c
index 6be9b33..4f620f2 100644
--- a/arch/powerpc/platforms/85xx/twr_p102x.c
+++ b/arch/powerpc/platforms/85xx/twr_p102x.c
@@ -23,7 +23,6 @@
#include <asm/udbg.h>
#include <asm/mpic.h>
#include <soc/fsl/qe/qe.h>
-#include <soc/fsl/qe/qe_ic.h>
#include <sysdev/fsl_soc.h>
#include <sysdev/fsl_pci.h>
diff --git a/drivers/irqchip/irq-qeic.c b/drivers/irqchip/irq-qeic.c
index a2d8084..26bfcbd 100644
--- a/drivers/irqchip/irq-qeic.c
+++ b/drivers/irqchip/irq-qeic.c
@@ -18,8 +18,11 @@
#include <linux/of_address.h>
#include <linux/kernel.h>
#include <linux/init.h>
+#include <linux/irqdomain.h>
#include <linux/irqchip.h>
#include <linux/errno.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
#include <linux/reboot.h>
#include <linux/slab.h>
#include <linux/stddef.h>
@@ -27,9 +30,8 @@
#include <linux/signal.h>
#include <linux/device.h>
#include <linux/spinlock.h>
-#include <asm/irq.h>
+#include <linux/irq.h>
#include <asm/io.h>
-#include <soc/fsl/qe/qe_ic.h>
#define NR_QE_IC_INTS 64
@@ -87,6 +89,43 @@
#define SIGNAL_HIGH 2
#define SIGNAL_LOW 0
+#define NUM_OF_QE_IC_GROUPS 6
+
+/* Flags when we init the QE IC */
+#define QE_IC_SPREADMODE_GRP_W 0x00000001
+#define QE_IC_SPREADMODE_GRP_X 0x00000002
+#define QE_IC_SPREADMODE_GRP_Y 0x00000004
+#define QE_IC_SPREADMODE_GRP_Z 0x00000008
+#define QE_IC_SPREADMODE_GRP_RISCA 0x00000010
+#define QE_IC_SPREADMODE_GRP_RISCB 0x00000020
+
+#define QE_IC_LOW_SIGNAL 0x00000100
+#define QE_IC_HIGH_SIGNAL 0x00000200
+
+#define QE_IC_GRP_W_PRI0_DEST_SIGNAL_HIGH 0x00001000
+#define QE_IC_GRP_W_PRI1_DEST_SIGNAL_HIGH 0x00002000
+#define QE_IC_GRP_X_PRI0_DEST_SIGNAL_HIGH 0x00004000
+#define QE_IC_GRP_X_PRI1_DEST_SIGNAL_HIGH 0x00008000
+#define QE_IC_GRP_Y_PRI0_DEST_SIGNAL_HIGH 0x00010000
+#define QE_IC_GRP_Y_PRI1_DEST_SIGNAL_HIGH 0x00020000
+#define QE_IC_GRP_Z_PRI0_DEST_SIGNAL_HIGH 0x00040000
+#define QE_IC_GRP_Z_PRI1_DEST_SIGNAL_HIGH 0x00080000
+#define QE_IC_GRP_RISCA_PRI0_DEST_SIGNAL_HIGH 0x00100000
+#define QE_IC_GRP_RISCA_PRI1_DEST_SIGNAL_HIGH 0x00200000
+#define QE_IC_GRP_RISCB_PRI0_DEST_SIGNAL_HIGH 0x00400000
+#define QE_IC_GRP_RISCB_PRI1_DEST_SIGNAL_HIGH 0x00800000
+#define QE_IC_GRP_W_DEST_SIGNAL_SHIFT (12)
+
+/* QE interrupt sources groups */
+enum qe_ic_grp_id {
+ QE_IC_GRP_W = 0, /* QE interrupt controller group W */
+ QE_IC_GRP_X, /* QE interrupt controller group X */
+ QE_IC_GRP_Y, /* QE interrupt controller group Y */
+ QE_IC_GRP_Z, /* QE interrupt controller group Z */
+ QE_IC_GRP_RISCA, /* QE interrupt controller RISC group A */
+ QE_IC_GRP_RISCB /* QE interrupt controller RISC group B */
+};
+
struct qe_ic {
/* Control registers offset */
u32 __iomem *regs;
@@ -265,15 +304,15 @@ static struct qe_ic_info qe_ic_info[] = {
},
};
-static inline u32 qe_ic_read(volatile __be32 __iomem * base, unsigned int reg)
+static u32 qe_ic_read(__be32 __iomem *base, unsigned int reg)
{
- return in_be32(base + (reg >> 2));
+ return ioread32be(base + (reg >> 2));
}
-static inline void qe_ic_write(volatile __be32 __iomem * base, unsigned int reg,
+static void qe_ic_write(__be32 __iomem *base, unsigned int reg,
u32 value)
{
- out_be32(base + (reg >> 2), value);
+ iowrite32be(value, base + (reg >> 2));
}
static inline struct qe_ic *qe_ic_from_irq(unsigned int virq)
@@ -375,8 +414,8 @@ static const struct irq_domain_ops qe_ic_host_ops = {
.xlate = irq_domain_xlate_onetwocell,
};
-/* Return an interrupt vector or NO_IRQ if no interrupt is pending. */
-unsigned int qe_ic_get_low_irq(struct qe_ic *qe_ic)
+/* Return an interrupt vector or 0 if no interrupt is pending. */
+static unsigned int qe_ic_get_low_irq(struct qe_ic *qe_ic)
{
int irq;
@@ -386,13 +425,13 @@ unsigned int qe_ic_get_low_irq(struct qe_ic *qe_ic)
irq = qe_ic_read(qe_ic->regs, QEIC_CIVEC) >> 26;
if (irq == 0)
- return NO_IRQ;
+ return 0;
return irq_linear_revmap(qe_ic->irqhost, irq);
}
-/* Return an interrupt vector or NO_IRQ if no interrupt is pending. */
-unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic)
+/* Return an interrupt vector or 0 if no interrupt is pending. */
+static unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic)
{
int irq;
@@ -402,11 +441,38 @@ unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic)
irq = qe_ic_read(qe_ic->regs, QEIC_CHIVEC) >> 26;
if (irq == 0)
- return NO_IRQ;
+ return 0;
return irq_linear_revmap(qe_ic->irqhost, irq);
}
+static void qe_ic_cascade_mpic(struct irq_desc *desc, int is_high)
+{
+ struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
+ struct irq_chip *chip = irq_desc_get_chip(desc);
+ unsigned int cascade_irq;
+
+ if (is_high)
+ cascade_irq = qe_ic_get_high_irq(qe_ic);
+ else
+ cascade_irq = qe_ic_get_low_irq(qe_ic);
+
+ if (cascade_irq != 0)
+ generic_handle_irq(cascade_irq);
+
+ chip->irq_eoi(&desc->irq_data);
+}
+
+static void qe_ic_cascade_low_mpic(struct irq_desc *desc)
+{
+ qe_ic_cascade_mpic(desc, 0);
+}
+
+static void qe_ic_cascade_high_mpic(struct irq_desc *desc)
+{
+ qe_ic_cascade_mpic(desc, 1);
+}
+
static int __init qe_ic_init(struct device_node *node, unsigned int flags)
{
struct qe_ic *qe_ic;
@@ -443,7 +509,7 @@ static int __init qe_ic_init(struct device_node *node, unsigned int flags)
qe_ic->virq_high = irq_of_parse_and_map(node, 0);
qe_ic->virq_low = irq_of_parse_and_map(node, 1);
- if (qe_ic->virq_low == NO_IRQ) {
+ if (qe_ic->virq_low == 0) {
pr_err("Failed to map QE_IC low IRQ\n");
ret = -ENOMEM;
goto err_domain_remove;
@@ -475,7 +541,7 @@ static int __init qe_ic_init(struct device_node *node, unsigned int flags)
irq_set_handler_data(qe_ic->virq_low, qe_ic);
irq_set_chained_handler(qe_ic->virq_low, qe_ic_cascade_low_mpic);
- if (qe_ic->virq_high != NO_IRQ &&
+ if (qe_ic->virq_high != 0 &&
qe_ic->virq_high != qe_ic->virq_low) {
irq_set_handler_data(qe_ic->virq_high, qe_ic);
irq_set_chained_handler(qe_ic->virq_high,
@@ -493,100 +559,6 @@ static int __init qe_ic_init(struct device_node *node, unsigned int flags)
return ret;
}
-void qe_ic_set_highest_priority(unsigned int virq, int high)
-{
- struct qe_ic *qe_ic = qe_ic_from_irq(virq);
- unsigned int src = virq_to_hw(virq);
- u32 temp = 0;
-
- temp = qe_ic_read(qe_ic->regs, QEIC_CICR);
-
- temp &= ~CICR_HP_MASK;
- temp |= src << CICR_HP_SHIFT;
-
- temp &= ~CICR_HPIT_MASK;
- temp |= (high ? SIGNAL_HIGH : SIGNAL_LOW) << CICR_HPIT_SHIFT;
-
- qe_ic_write(qe_ic->regs, QEIC_CICR, temp);
-}
-
-/* Set Priority level within its group, from 1 to 8 */
-int qe_ic_set_priority(unsigned int virq, unsigned int priority)
-{
- struct qe_ic *qe_ic = qe_ic_from_irq(virq);
- unsigned int src = virq_to_hw(virq);
- u32 temp;
-
- if (priority > 8 || priority == 0)
- return -EINVAL;
- if (WARN_ONCE(src >= ARRAY_SIZE(qe_ic_info),
- "%s: Invalid hw irq number for QEIC\n", __func__))
- return -EINVAL;
- if (qe_ic_info[src].pri_reg == 0)
- return -EINVAL;
-
- temp = qe_ic_read(qe_ic->regs, qe_ic_info[src].pri_reg);
-
- if (priority < 4) {
- temp &= ~(0x7 << (32 - priority * 3));
- temp |= qe_ic_info[src].pri_code << (32 - priority * 3);
- } else {
- temp &= ~(0x7 << (24 - priority * 3));
- temp |= qe_ic_info[src].pri_code << (24 - priority * 3);
- }
-
- qe_ic_write(qe_ic->regs, qe_ic_info[src].pri_reg, temp);
-
- return 0;
-}
-
-/* Set a QE priority to use high irq, only priority 1~2 can use high irq */
-int qe_ic_set_high_priority(unsigned int virq, unsigned int priority, int high)
-{
- struct qe_ic *qe_ic = qe_ic_from_irq(virq);
- unsigned int src = virq_to_hw(virq);
- u32 temp, control_reg = QEIC_CICNR, shift = 0;
-
- if (priority > 2 || priority == 0)
- return -EINVAL;
- if (WARN_ONCE(src >= ARRAY_SIZE(qe_ic_info),
- "%s: Invalid hw irq number for QEIC\n", __func__))
- return -EINVAL;
-
- switch (qe_ic_info[src].pri_reg) {
- case QEIC_CIPZCC:
- shift = CICNR_ZCC1T_SHIFT;
- break;
- case QEIC_CIPWCC:
- shift = CICNR_WCC1T_SHIFT;
- break;
- case QEIC_CIPYCC:
- shift = CICNR_YCC1T_SHIFT;
- break;
- case QEIC_CIPXCC:
- shift = CICNR_XCC1T_SHIFT;
- break;
- case QEIC_CIPRTA:
- shift = CRICR_RTA1T_SHIFT;
- control_reg = QEIC_CRICR;
- break;
- case QEIC_CIPRTB:
- shift = CRICR_RTB1T_SHIFT;
- control_reg = QEIC_CRICR;
- break;
- default:
- return -EINVAL;
- }
-
- shift += (2 - priority) * 2;
- temp = qe_ic_read(qe_ic->regs, control_reg);
- temp &= ~(SIGNAL_MASK << shift);
- temp |= (high ? SIGNAL_HIGH : SIGNAL_LOW) << shift;
- qe_ic_write(qe_ic->regs, control_reg, temp);
-
- return 0;
-}
-
static int __init init_qe_ic(struct device_node *node,
struct device_node *parent)
{
diff --git a/include/soc/fsl/qe/qe_ic.h b/include/soc/fsl/qe/qe_ic.h
deleted file mode 100644
index 6113699..0000000
--- a/include/soc/fsl/qe/qe_ic.h
+++ /dev/null
@@ -1,132 +0,0 @@
-/*
- * Copyright (C) 2006 Freescale Semiconductor, Inc. All rights reserved.
- *
- * Authors: Shlomi Gridish <gridish@freescale.com>
- * Li Yang <leoli@freescale.com>
- *
- * Description:
- * QE IC external definitions and structure.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- */
-#ifndef _ASM_POWERPC_QE_IC_H
-#define _ASM_POWERPC_QE_IC_H
-
-#include <linux/irq.h>
-
-struct device_node;
-struct qe_ic;
-
-#define NUM_OF_QE_IC_GROUPS 6
-
-/* Flags when we init the QE IC */
-#define QE_IC_SPREADMODE_GRP_W 0x00000001
-#define QE_IC_SPREADMODE_GRP_X 0x00000002
-#define QE_IC_SPREADMODE_GRP_Y 0x00000004
-#define QE_IC_SPREADMODE_GRP_Z 0x00000008
-#define QE_IC_SPREADMODE_GRP_RISCA 0x00000010
-#define QE_IC_SPREADMODE_GRP_RISCB 0x00000020
-
-#define QE_IC_LOW_SIGNAL 0x00000100
-#define QE_IC_HIGH_SIGNAL 0x00000200
-
-#define QE_IC_GRP_W_PRI0_DEST_SIGNAL_HIGH 0x00001000
-#define QE_IC_GRP_W_PRI1_DEST_SIGNAL_HIGH 0x00002000
-#define QE_IC_GRP_X_PRI0_DEST_SIGNAL_HIGH 0x00004000
-#define QE_IC_GRP_X_PRI1_DEST_SIGNAL_HIGH 0x00008000
-#define QE_IC_GRP_Y_PRI0_DEST_SIGNAL_HIGH 0x00010000
-#define QE_IC_GRP_Y_PRI1_DEST_SIGNAL_HIGH 0x00020000
-#define QE_IC_GRP_Z_PRI0_DEST_SIGNAL_HIGH 0x00040000
-#define QE_IC_GRP_Z_PRI1_DEST_SIGNAL_HIGH 0x00080000
-#define QE_IC_GRP_RISCA_PRI0_DEST_SIGNAL_HIGH 0x00100000
-#define QE_IC_GRP_RISCA_PRI1_DEST_SIGNAL_HIGH 0x00200000
-#define QE_IC_GRP_RISCB_PRI0_DEST_SIGNAL_HIGH 0x00400000
-#define QE_IC_GRP_RISCB_PRI1_DEST_SIGNAL_HIGH 0x00800000
-#define QE_IC_GRP_W_DEST_SIGNAL_SHIFT (12)
-
-/* QE interrupt sources groups */
-enum qe_ic_grp_id {
- QE_IC_GRP_W = 0, /* QE interrupt controller group W */
- QE_IC_GRP_X, /* QE interrupt controller group X */
- QE_IC_GRP_Y, /* QE interrupt controller group Y */
- QE_IC_GRP_Z, /* QE interrupt controller group Z */
- QE_IC_GRP_RISCA, /* QE interrupt controller RISC group A */
- QE_IC_GRP_RISCB /* QE interrupt controller RISC group B */
-};
-
-#ifdef CONFIG_QUICC_ENGINE
-unsigned int qe_ic_get_low_irq(struct qe_ic *qe_ic);
-unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic);
-#else
-static inline unsigned int qe_ic_get_low_irq(struct qe_ic *qe_ic)
-{ return 0; }
-static inline unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic)
-{ return 0; }
-#endif /* CONFIG_QUICC_ENGINE */
-
-void qe_ic_set_highest_priority(unsigned int virq, int high);
-int qe_ic_set_priority(unsigned int virq, unsigned int priority);
-int qe_ic_set_high_priority(unsigned int virq, unsigned int priority, int high);
-
-static inline void qe_ic_cascade_low_ipic(struct irq_desc *desc)
-{
- struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
- unsigned int cascade_irq = qe_ic_get_low_irq(qe_ic);
-
- if (cascade_irq != NO_IRQ)
- generic_handle_irq(cascade_irq);
-}
-
-static inline void qe_ic_cascade_high_ipic(struct irq_desc *desc)
-{
- struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
- unsigned int cascade_irq = qe_ic_get_high_irq(qe_ic);
-
- if (cascade_irq != NO_IRQ)
- generic_handle_irq(cascade_irq);
-}
-
-static inline void qe_ic_cascade_low_mpic(struct irq_desc *desc)
-{
- struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
- unsigned int cascade_irq = qe_ic_get_low_irq(qe_ic);
- struct irq_chip *chip = irq_desc_get_chip(desc);
-
- if (cascade_irq != NO_IRQ)
- generic_handle_irq(cascade_irq);
-
- chip->irq_eoi(&desc->irq_data);
-}
-
-static inline void qe_ic_cascade_high_mpic(struct irq_desc *desc)
-{
- struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
- unsigned int cascade_irq = qe_ic_get_high_irq(qe_ic);
- struct irq_chip *chip = irq_desc_get_chip(desc);
-
- if (cascade_irq != NO_IRQ)
- generic_handle_irq(cascade_irq);
-
- chip->irq_eoi(&desc->irq_data);
-}
-
-static inline void qe_ic_cascade_muxed_mpic(struct irq_desc *desc)
-{
- struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
- unsigned int cascade_irq;
- struct irq_chip *chip = irq_desc_get_chip(desc);
-
- cascade_irq = qe_ic_get_high_irq(qe_ic);
- if (cascade_irq == NO_IRQ)
- cascade_irq = qe_ic_get_low_irq(qe_ic);
-
- if (cascade_irq != NO_IRQ)
- generic_handle_irq(cascade_irq);
-
- chip->irq_eoi(&desc->irq_data);
-}
-
-#endif /* _ASM_POWERPC_QE_IC_H */
--
2.1.0.27.g96db324
^ permalink raw reply related [flat|nested] 16+ messages in thread* Re: [PATCH v10 4/4] irqchip/qeic: remove PPCisms for QEIC
2017-08-07 3:07 ` [PATCH v10 4/4] irqchip/qeic: remove PPCisms for QEIC Zhao Qiang
@ 2017-08-07 7:02 ` Michael Ellerman
2017-08-08 6:21 ` Qiang Zhao
0 siblings, 1 reply; 16+ messages in thread
From: Michael Ellerman @ 2017-08-07 7:02 UTC (permalink / raw)
To: Zhao Qiang, tglx; +Cc: oss, Zhao Qiang, linuxppc-dev, xiaobo.xie, linux-kernel
Zhao Qiang <qiang.zhao@nxp.com> writes:
> QEIC was supported on PowerPC, and dependent on PPC,
> Now it is supported on other platforms, so remove PPCisms.
>
> Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
> ---
> arch/powerpc/platforms/83xx/km83xx.c | 1 -
> arch/powerpc/platforms/83xx/misc.c | 1 -
> arch/powerpc/platforms/83xx/mpc832x_mds.c | 1 -
> arch/powerpc/platforms/83xx/mpc832x_rdb.c | 1 -
> arch/powerpc/platforms/83xx/mpc836x_mds.c | 1 -
> arch/powerpc/platforms/83xx/mpc836x_rdk.c | 1 -
> arch/powerpc/platforms/85xx/corenet_generic.c | 1 -
> arch/powerpc/platforms/85xx/mpc85xx_mds.c | 1 -
> arch/powerpc/platforms/85xx/mpc85xx_rdb.c | 1 -
> arch/powerpc/platforms/85xx/twr_p102x.c | 1 -
> drivers/irqchip/irq-qeic.c | 188 +++++++++++---------------
> include/soc/fsl/qe/qe_ic.h | 132 ------------------
> 12 files changed, 80 insertions(+), 250 deletions(-)
> delete mode 100644 include/soc/fsl/qe/qe_ic.h
>
> diff --git a/arch/powerpc/platforms/83xx/km83xx.c b/arch/powerpc/platforms/83xx/km83xx.c
> index d8642a4..b1cef0a 100644
> --- a/arch/powerpc/platforms/83xx/km83xx.c
> +++ b/arch/powerpc/platforms/83xx/km83xx.c
> @@ -38,7 +38,6 @@
> #include <sysdev/fsl_soc.h>
> #include <sysdev/fsl_pci.h>
> #include <soc/fsl/qe/qe.h>
> -#include <soc/fsl/qe/qe_ic.h>
You deleted that file in patch 2. So didn't you just break the build for
the last two commits?
cheers
^ permalink raw reply [flat|nested] 16+ messages in thread
* RE: [PATCH v10 4/4] irqchip/qeic: remove PPCisms for QEIC
2017-08-07 7:02 ` Michael Ellerman
@ 2017-08-08 6:21 ` Qiang Zhao
2017-08-08 10:04 ` Michael Ellerman
0 siblings, 1 reply; 16+ messages in thread
From: Qiang Zhao @ 2017-08-08 6:21 UTC (permalink / raw)
To: Michael Ellerman, tglx@linutronix.de
Cc: oss@buserror.net, linuxppc-dev@lists.ozlabs.org, Xiaobo Xie,
linux-kernel@vger.kernel.org
On Mon 8/7/2017 3:02 PM, Michael Ellerman <mpe@ellerman.id.au> wrote:
> -----Original Message-----
> From: Michael Ellerman [mailto:mpe@ellerman.id.au]
> Sent: Monday, August 07, 2017 3:02 PM
> To: Qiang Zhao <qiang.zhao@nxp.com>; tglx@linutronix.de
> Cc: oss@buserror.net; Qiang Zhao <qiang.zhao@nxp.com>; linuxppc-
> dev@lists.ozlabs.org; Xiaobo Xie <xiaobo.xie@nxp.com>; linux-
> kernel@vger.kernel.org
> Subject: Re: [PATCH v10 4/4] irqchip/qeic: remove PPCisms for QEIC
>=20
> Zhao Qiang <qiang.zhao@nxp.com> writes:
>=20
> > QEIC was supported on PowerPC, and dependent on PPC, Now it is
> > supported on other platforms, so remove PPCisms.
> >
> > Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
> > ---
> > arch/powerpc/platforms/83xx/km83xx.c | 1 -
> > arch/powerpc/platforms/83xx/misc.c | 1 -
> > arch/powerpc/platforms/83xx/mpc832x_mds.c | 1 -
> > arch/powerpc/platforms/83xx/mpc832x_rdb.c | 1 -
> > arch/powerpc/platforms/83xx/mpc836x_mds.c | 1 -
> > arch/powerpc/platforms/83xx/mpc836x_rdk.c | 1 -
> > arch/powerpc/platforms/85xx/corenet_generic.c | 1 -
> > arch/powerpc/platforms/85xx/mpc85xx_mds.c | 1 -
> > arch/powerpc/platforms/85xx/mpc85xx_rdb.c | 1 -
> > arch/powerpc/platforms/85xx/twr_p102x.c | 1 -
> > drivers/irqchip/irq-qeic.c | 188 +++++++++++-------=
--------
> > include/soc/fsl/qe/qe_ic.h | 132 ------------------
> > 12 files changed, 80 insertions(+), 250 deletions(-) delete mode
> > 100644 include/soc/fsl/qe/qe_ic.h
> >
> > diff --git a/arch/powerpc/platforms/83xx/km83xx.c
> > b/arch/powerpc/platforms/83xx/km83xx.c
> > index d8642a4..b1cef0a 100644
> > --- a/arch/powerpc/platforms/83xx/km83xx.c
> > +++ b/arch/powerpc/platforms/83xx/km83xx.c
> > @@ -38,7 +38,6 @@
> > #include <sysdev/fsl_soc.h>
> > #include <sysdev/fsl_pci.h>
> > #include <soc/fsl/qe/qe.h>
> > -#include <soc/fsl/qe/qe_ic.h>
>=20
> You deleted that file in patch 2. So didn't you just break the build for =
the last two
> commits?
Sorry, I am not sure what you said. Could you explain?
Thank you!
BR
Qiang Zhao
^ permalink raw reply [flat|nested] 16+ messages in thread
* RE: [PATCH v10 4/4] irqchip/qeic: remove PPCisms for QEIC
2017-08-08 6:21 ` Qiang Zhao
@ 2017-08-08 10:04 ` Michael Ellerman
2017-08-09 2:35 ` Qiang Zhao
0 siblings, 1 reply; 16+ messages in thread
From: Michael Ellerman @ 2017-08-08 10:04 UTC (permalink / raw)
To: Qiang Zhao, tglx@linutronix.de
Cc: oss@buserror.net, linuxppc-dev@lists.ozlabs.org, Xiaobo Xie,
linux-kernel@vger.kernel.org
Qiang Zhao <qiang.zhao@nxp.com> writes:
> On Mon 8/7/2017 3:02 PM, Michael Ellerman <mpe@ellerman.id.au> wrote:
>
>> -----Original Message-----
>> From: Michael Ellerman [mailto:mpe@ellerman.id.au]
>> Sent: Monday, August 07, 2017 3:02 PM
>> To: Qiang Zhao <qiang.zhao@nxp.com>; tglx@linutronix.de
>> Cc: oss@buserror.net; Qiang Zhao <qiang.zhao@nxp.com>; linuxppc-
>> dev@lists.ozlabs.org; Xiaobo Xie <xiaobo.xie@nxp.com>; linux-
>> kernel@vger.kernel.org
>> Subject: Re: [PATCH v10 4/4] irqchip/qeic: remove PPCisms for QEIC
>>
>> Zhao Qiang <qiang.zhao@nxp.com> writes:
>>
>> > QEIC was supported on PowerPC, and dependent on PPC, Now it is
>> > supported on other platforms, so remove PPCisms.
>> >
>> > Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
>> > ---
>> > arch/powerpc/platforms/83xx/km83xx.c | 1 -
>> > arch/powerpc/platforms/83xx/misc.c | 1 -
>> > arch/powerpc/platforms/83xx/mpc832x_mds.c | 1 -
>> > arch/powerpc/platforms/83xx/mpc832x_rdb.c | 1 -
>> > arch/powerpc/platforms/83xx/mpc836x_mds.c | 1 -
>> > arch/powerpc/platforms/83xx/mpc836x_rdk.c | 1 -
>> > arch/powerpc/platforms/85xx/corenet_generic.c | 1 -
>> > arch/powerpc/platforms/85xx/mpc85xx_mds.c | 1 -
>> > arch/powerpc/platforms/85xx/mpc85xx_rdb.c | 1 -
>> > arch/powerpc/platforms/85xx/twr_p102x.c | 1 -
>> > drivers/irqchip/irq-qeic.c | 188 +++++++++++---------------
>> > include/soc/fsl/qe/qe_ic.h | 132 ------------------
>> > 12 files changed, 80 insertions(+), 250 deletions(-) delete mode
>> > 100644 include/soc/fsl/qe/qe_ic.h
>> >
>> > diff --git a/arch/powerpc/platforms/83xx/km83xx.c
>> > b/arch/powerpc/platforms/83xx/km83xx.c
>> > index d8642a4..b1cef0a 100644
>> > --- a/arch/powerpc/platforms/83xx/km83xx.c
>> > +++ b/arch/powerpc/platforms/83xx/km83xx.c
>> > @@ -38,7 +38,6 @@
>> > #include <sysdev/fsl_soc.h>
>> > #include <sysdev/fsl_pci.h>
>> > #include <soc/fsl/qe/qe.h>
>> > -#include <soc/fsl/qe/qe_ic.h>
>>
>> You deleted that file in patch 2. So didn't you just break the build for the last two
>> commits?
>
> Sorry, I am not sure what you said. Could you explain?
Don't worry about it. I was confused by the fact that we have both:
drivers/soc/fsl/qe/qe_ic.h
and:
include/soc/fsl/qe/qe_ic.h
cheers
^ permalink raw reply [flat|nested] 16+ messages in thread
* RE: [PATCH v10 4/4] irqchip/qeic: remove PPCisms for QEIC
2017-08-08 10:04 ` Michael Ellerman
@ 2017-08-09 2:35 ` Qiang Zhao
0 siblings, 0 replies; 16+ messages in thread
From: Qiang Zhao @ 2017-08-09 2:35 UTC (permalink / raw)
To: Michael Ellerman, tglx@linutronix.de
Cc: oss@buserror.net, linuxppc-dev@lists.ozlabs.org, Xiaobo Xie,
linux-kernel@vger.kernel.org
On Tue 8/8/2017 6:05 PM, Michael Ellerman <mpe@ellerman.id.au> wrote:
> -----Original Message-----
> From: Michael Ellerman [mailto:mpe@ellerman.id.au]
> Sent: Tuesday, August 08, 2017 6:05 PM
> To: Qiang Zhao <qiang.zhao@nxp.com>; tglx@linutronix.de
> Cc: oss@buserror.net; linuxppc-dev@lists.ozlabs.org; Xiaobo Xie
> <xiaobo.xie@nxp.com>; linux-kernel@vger.kernel.org
> Subject: RE: [PATCH v10 4/4] irqchip/qeic: remove PPCisms for QEIC
>=20
> Qiang Zhao <qiang.zhao@nxp.com> writes:
>=20
> > On Mon 8/7/2017 3:02 PM, Michael Ellerman <mpe@ellerman.id.au> wrote:
> >
> >> -----Original Message-----
> >> From: Michael Ellerman [mailto:mpe@ellerman.id.au]
> >> Sent: Monday, August 07, 2017 3:02 PM
> >> To: Qiang Zhao <qiang.zhao@nxp.com>; tglx@linutronix.de
> >> Cc: oss@buserror.net; Qiang Zhao <qiang.zhao@nxp.com>; linuxppc-
> >> dev@lists.ozlabs.org; Xiaobo Xie <xiaobo.xie@nxp.com>; linux-
> >> kernel@vger.kernel.org
> >> Subject: Re: [PATCH v10 4/4] irqchip/qeic: remove PPCisms for QEIC
> >>
> >> Zhao Qiang <qiang.zhao@nxp.com> writes:
> >>
> >> > QEIC was supported on PowerPC, and dependent on PPC, Now it is
> >> > supported on other platforms, so remove PPCisms.
> >> >
> >> > Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
> >> > ---
> >> > arch/powerpc/platforms/83xx/km83xx.c | 1 -
> >> > arch/powerpc/platforms/83xx/misc.c | 1 -
> >> > arch/powerpc/platforms/83xx/mpc832x_mds.c | 1 -
> >> > arch/powerpc/platforms/83xx/mpc832x_rdb.c | 1 -
> >> > arch/powerpc/platforms/83xx/mpc836x_mds.c | 1 -
> >> > arch/powerpc/platforms/83xx/mpc836x_rdk.c | 1 -
> >> > arch/powerpc/platforms/85xx/corenet_generic.c | 1 -
> >> > arch/powerpc/platforms/85xx/mpc85xx_mds.c | 1 -
> >> > arch/powerpc/platforms/85xx/mpc85xx_rdb.c | 1 -
> >> > arch/powerpc/platforms/85xx/twr_p102x.c | 1 -
> >> > drivers/irqchip/irq-qeic.c | 188 +++++++++++----=
-----------
> >> > include/soc/fsl/qe/qe_ic.h | 132 ---------------=
---
> >> > 12 files changed, 80 insertions(+), 250 deletions(-) delete mode
> >> > 100644 include/soc/fsl/qe/qe_ic.h
> >> >
> >> > diff --git a/arch/powerpc/platforms/83xx/km83xx.c
> >> > b/arch/powerpc/platforms/83xx/km83xx.c
> >> > index d8642a4..b1cef0a 100644
> >> > --- a/arch/powerpc/platforms/83xx/km83xx.c
> >> > +++ b/arch/powerpc/platforms/83xx/km83xx.c
> >> > @@ -38,7 +38,6 @@
> >> > #include <sysdev/fsl_soc.h>
> >> > #include <sysdev/fsl_pci.h>
> >> > #include <soc/fsl/qe/qe.h>
> >> > -#include <soc/fsl/qe/qe_ic.h>
> >>
> >> You deleted that file in patch 2. So didn't you just break the build
> >> for the last two commits?
> >
> > Sorry, I am not sure what you said. Could you explain?
>=20
> Don't worry about it. I was confused by the fact that we have both:
>=20
> drivers/soc/fsl/qe/qe_ic.h
>=20
> and:
>=20
> include/soc/fsl/qe/qe_ic.h
>=20
> cheers
I think this is a issue left over by history.
In patch with commit id 7aa1aa6ecec2af19d9aa85430ce3e56119e21626, I just mo=
ve them out from arch/powerpc. =20
Maybe need to ask the original author why there are 2 qe_ic.h.
Best Regards
Qiang Zhao
^ permalink raw reply [flat|nested] 16+ messages in thread
* RE: [PATCH v10 0/4] this patchset is to remove PPCisms for QEIC
2017-08-07 3:07 [PATCH v10 0/4] this patchset is to remove PPCisms for QEIC Zhao Qiang
` (3 preceding siblings ...)
2017-08-07 3:07 ` [PATCH v10 4/4] irqchip/qeic: remove PPCisms for QEIC Zhao Qiang
@ 2017-10-24 1:51 ` Qiang Zhao
2017-10-31 3:06 ` Qiang Zhao
4 siblings, 1 reply; 16+ messages in thread
From: Qiang Zhao @ 2017-10-24 1:51 UTC (permalink / raw)
To: Qiang Zhao, tglx@linutronix.de
Cc: oss@buserror.net, Xiaobo Xie, linux-kernel@vger.kernel.org,
linuxppc-dev@lists.ozlabs.org
Hi all,
Could anybody review this patchset and take action on them? Thank you!
Best Regards
Qiang Zhao
> -----Original Message-----
> From: Zhao Qiang [mailto:qiang.zhao@nxp.com]
> Sent: Monday, August 07, 2017 11:07 AM
> To: tglx@linutronix.de
> Cc: oss@buserror.net; Xiaobo Xie <xiaobo.xie@nxp.com>; linux-
> kernel@vger.kernel.org; linuxppc-dev@lists.ozlabs.org; Qiang Zhao
> <qiang.zhao@nxp.com>
> Subject: [PATCH v10 0/4] this patchset is to remove PPCisms for QEIC
>=20
> QEIC is supported more than just powerpc boards, so remove PPCisms.
>=20
> changelog:
> Changes for v8:
> - use IRQCHIP_DECLARE() instead of subsys_initcall in qeic driver
> - remove include/soc/fsl/qe/qe_ic.h
> Changes for v9:
> - rebase
> - fix the compile issue when apply the second patch, in fact, there was
> no compile issue
> when apply all the patches of this patchset
> Changes for v10:
> - simplify codes, remove duplicated codes
>=20
> Zhao Qiang (4):
> irqchip/qeic: move qeic driver from drivers/soc/fsl/qe
> Changes for v2:
> - modify the subject and commit msg
> Changes for v3:
> - merge .h file to .c, rename it with irq-qeic.c
> Changes for v4:
> - modify comments
> Changes for v5:
> - disable rename detection
> Changes for v6:
> - rebase
> Changes for v7:
> - na
>=20
> irqchip/qeic: merge qeic init code from platforms to a common function
> Changes for v2:
> - modify subject and commit msg
> - add check for qeic by type
> Changes for v3:
> - na
> Changes for v4:
> - na
> Changes for v5:
> - na
> Changes for v6:
> - rebase
> Changes for v7:
> - na
> Changes for v8:
> - use IRQCHIP_DECLARE() instead of subsys_initcall
>=20
> irqchip/qeic: merge qeic_of_init into qe_ic_init
> Changes for v2:
> - modify subject and commit msg
> - return 0 and add put node when return in qe_ic_init
> Changes for v3:
> - na
> Changes for v4:
> - na
> Changes for v5:
> - na
> Changes for v6:
> - rebase
> Changes for v7:
> - na
>=20
> irqchip/qeic: remove PPCisms for QEIC
> Changes for v6:
> - new added
> Changes for v7:
> - fix warning
> Changes for v8:
> - remove include/soc/fsl/qe/qe_ic.h
>=20
> Zhao Qiang (4):
> irqchip/qeic: move qeic driver from drivers/soc/fsl/qe
> irqchip/qeic: merge qeic init code from platforms to a common function
> irqchip/qeic: merge qeic_of_init into qe_ic_init
> irqchip/qeic: remove PPCisms for QEIC
>=20
> MAINTAINERS | 6 +
> arch/powerpc/platforms/83xx/km83xx.c | 1 -
> arch/powerpc/platforms/83xx/misc.c | 16 -
> arch/powerpc/platforms/83xx/mpc832x_mds.c | 1 -
> arch/powerpc/platforms/83xx/mpc832x_rdb.c | 1 -
> arch/powerpc/platforms/83xx/mpc836x_mds.c | 1 -
> arch/powerpc/platforms/83xx/mpc836x_rdk.c | 1 -
> arch/powerpc/platforms/85xx/corenet_generic.c | 10 -
> arch/powerpc/platforms/85xx/mpc85xx_mds.c | 15 -
> arch/powerpc/platforms/85xx/mpc85xx_rdb.c | 17 -
> arch/powerpc/platforms/85xx/twr_p102x.c | 15 -
> drivers/irqchip/Makefile | 1 +
> drivers/{soc/fsl/qe/qe_ic.c =3D> irqchip/irq-qeic.c} | 358 ++++++++++++-=
--------
> drivers/soc/fsl/qe/Makefile | 2 +-
> drivers/soc/fsl/qe/qe_ic.h | 103 ------
> include/soc/fsl/qe/qe_ic.h | 139 --------
> 16 files changed, 218 insertions(+), 469 deletions(-) rename
> drivers/{soc/fsl/qe/qe_ic.c =3D> irqchip/irq-qeic.c} (58%) delete mode 1=
00644
> drivers/soc/fsl/qe/qe_ic.h delete mode 100644 include/soc/fsl/qe/qe_ic.h
>=20
> --
> 2.1.0.27.g96db324
^ permalink raw reply [flat|nested] 16+ messages in thread* RE: [PATCH v10 0/4] this patchset is to remove PPCisms for QEIC
2017-10-24 1:51 ` [PATCH v10 0/4] this patchset is to " Qiang Zhao
@ 2017-10-31 3:06 ` Qiang Zhao
2017-11-01 0:54 ` Michael Ellerman
0 siblings, 1 reply; 16+ messages in thread
From: Qiang Zhao @ 2017-10-31 3:06 UTC (permalink / raw)
To: tglx@linutronix.de, Jason Cooper, Marc Zyngier
Cc: oss@buserror.net, Xiaobo Xie, linux-kernel@vger.kernel.org,
linuxppc-dev@lists.ozlabs.org
Hi all,
Could anybody review this patchset and take action on them? Thank you!
Best Regards
Qiang Zhao
> > -----Original Message-----
> > From: Zhao Qiang [mailto:qiang.zhao@nxp.com]
> > Sent: Monday, August 07, 2017 11:07 AM
> > To: tglx@linutronix.de
> > Cc: oss@buserror.net; Xiaobo Xie <xiaobo.xie@nxp.com>; linux-
> > kernel@vger.kernel.org; linuxppc-dev@lists.ozlabs.org; Qiang Zhao
> > <qiang.zhao@nxp.com>
> > Subject: [PATCH v10 0/4] this patchset is to remove PPCisms for QEIC
> >
> > QEIC is supported more than just powerpc boards, so remove PPCisms.
> >
> > changelog:
> > Changes for v8:
> > - use IRQCHIP_DECLARE() instead of subsys_initcall in qeic driver
> > - remove include/soc/fsl/qe/qe_ic.h
> > Changes for v9:
> > - rebase
> > - fix the compile issue when apply the second patch, in fact, there
> > was no compile issue
> > when apply all the patches of this patchset
> > Changes for v10:
> > - simplify codes, remove duplicated codes
> >
> > Zhao Qiang (4):
> > irqchip/qeic: move qeic driver from drivers/soc/fsl/qe
> > Changes for v2:
> > - modify the subject and commit msg
> > Changes for v3:
> > - merge .h file to .c, rename it with irq-qeic.c
> > Changes for v4:
> > - modify comments
> > Changes for v5:
> > - disable rename detection
> > Changes for v6:
> > - rebase
> > Changes for v7:
> > - na
> >
> > irqchip/qeic: merge qeic init code from platforms to a common functio=
n
> > Changes for v2:
> > - modify subject and commit msg
> > - add check for qeic by type
> > Changes for v3:
> > - na
> > Changes for v4:
> > - na
> > Changes for v5:
> > - na
> > Changes for v6:
> > - rebase
> > Changes for v7:
> > - na
> > Changes for v8:
> > - use IRQCHIP_DECLARE() instead of subsys_initcall
> >
> > irqchip/qeic: merge qeic_of_init into qe_ic_init
> > Changes for v2:
> > - modify subject and commit msg
> > - return 0 and add put node when return in qe_ic_init
> > Changes for v3:
> > - na
> > Changes for v4:
> > - na
> > Changes for v5:
> > - na
> > Changes for v6:
> > - rebase
> > Changes for v7:
> > - na
> >
> > irqchip/qeic: remove PPCisms for QEIC
> > Changes for v6:
> > - new added
> > Changes for v7:
> > - fix warning
> > Changes for v8:
> > - remove include/soc/fsl/qe/qe_ic.h
> >
> > Zhao Qiang (4):
> > irqchip/qeic: move qeic driver from drivers/soc/fsl/qe
> > irqchip/qeic: merge qeic init code from platforms to a common functio=
n
> > irqchip/qeic: merge qeic_of_init into qe_ic_init
> > irqchip/qeic: remove PPCisms for QEIC
> >
> > MAINTAINERS | 6 +
> > arch/powerpc/platforms/83xx/km83xx.c | 1 -
> > arch/powerpc/platforms/83xx/misc.c | 16 -
> > arch/powerpc/platforms/83xx/mpc832x_mds.c | 1 -
> > arch/powerpc/platforms/83xx/mpc832x_rdb.c | 1 -
> > arch/powerpc/platforms/83xx/mpc836x_mds.c | 1 -
> > arch/powerpc/platforms/83xx/mpc836x_rdk.c | 1 -
> > arch/powerpc/platforms/85xx/corenet_generic.c | 10 -
> > arch/powerpc/platforms/85xx/mpc85xx_mds.c | 15 -
> > arch/powerpc/platforms/85xx/mpc85xx_rdb.c | 17 -
> > arch/powerpc/platforms/85xx/twr_p102x.c | 15 -
> > drivers/irqchip/Makefile | 1 +
> > drivers/{soc/fsl/qe/qe_ic.c =3D> irqchip/irq-qeic.c} | 358 +++++++++++=
+---------
> > drivers/soc/fsl/qe/Makefile | 2 +-
> > drivers/soc/fsl/qe/qe_ic.h | 103 ------
> > include/soc/fsl/qe/qe_ic.h | 139 --------
> > 16 files changed, 218 insertions(+), 469 deletions(-) rename
> > drivers/{soc/fsl/qe/qe_ic.c =3D> irqchip/irq-qeic.c} (58%) delete mode
> > 100644 drivers/soc/fsl/qe/qe_ic.h delete mode 100644
> > include/soc/fsl/qe/qe_ic.h
> >
> > --
> > 2.1.0.27.g96db324
^ permalink raw reply [flat|nested] 16+ messages in thread* RE: [PATCH v10 0/4] this patchset is to remove PPCisms for QEIC
2017-10-31 3:06 ` Qiang Zhao
@ 2017-11-01 0:54 ` Michael Ellerman
2017-11-01 1:39 ` Qiang Zhao
0 siblings, 1 reply; 16+ messages in thread
From: Michael Ellerman @ 2017-11-01 0:54 UTC (permalink / raw)
To: Qiang Zhao, tglx@linutronix.de, Jason Cooper, Marc Zyngier
Cc: oss@buserror.net, linuxppc-dev@lists.ozlabs.org, Xiaobo Xie,
linux-kernel@vger.kernel.org
Qiang Zhao <qiang.zhao@nxp.com> writes:
> Hi all,
>
> Could anybody review this patchset and take action on them? Thank you!
Who maintains this? I don't actually know, it's not powerpc code, or is it?
cheers
^ permalink raw reply [flat|nested] 16+ messages in thread
* RE: [PATCH v10 0/4] this patchset is to remove PPCisms for QEIC
2017-11-01 0:54 ` Michael Ellerman
@ 2017-11-01 1:39 ` Qiang Zhao
2017-11-01 17:09 ` Thomas Gleixner
0 siblings, 1 reply; 16+ messages in thread
From: Qiang Zhao @ 2017-11-01 1:39 UTC (permalink / raw)
To: Michael Ellerman, tglx@linutronix.de, Jason Cooper, Marc Zyngier
Cc: oss@buserror.net, linuxppc-dev@lists.ozlabs.org, Xiaobo Xie,
linux-kernel@vger.kernel.org
Michael Ellerman <mpe@ellerman.id.au> wrote
>=20
> Qiang Zhao <qiang.zhao@nxp.com> writes:
>=20
> > Hi all,
> >
> > Could anybody review this patchset and take action on them? Thank you!
>=20
> Who maintains this? I don't actually know, it's not powerpc code, or is i=
t?
Yes, it's not powerpc code, it is irqchip code, maintained by Thomas, Jason=
and Marc according to MAINTAINERS file.
Hi Thomas, Jason and Marc,
Could you keep an eye on this patchset? Thank you!
Best Regards
Qiang Zhao
^ permalink raw reply [flat|nested] 16+ messages in thread
* RE: [PATCH v10 0/4] this patchset is to remove PPCisms for QEIC
2017-11-01 1:39 ` Qiang Zhao
@ 2017-11-01 17:09 ` Thomas Gleixner
2017-11-02 1:41 ` Qiang Zhao
2017-11-02 10:12 ` Marc Zyngier
0 siblings, 2 replies; 16+ messages in thread
From: Thomas Gleixner @ 2017-11-01 17:09 UTC (permalink / raw)
To: Qiang Zhao
Cc: Michael Ellerman, Jason Cooper, Marc Zyngier, oss@buserror.net,
linuxppc-dev@lists.ozlabs.org, Xiaobo Xie,
linux-kernel@vger.kernel.org
On Wed, 1 Nov 2017, Qiang Zhao wrote:
> Michael Ellerman <mpe@ellerman.id.au> wrote
> >
> > Qiang Zhao <qiang.zhao@nxp.com> writes:
> >
> > > Hi all,
> > >
> > > Could anybody review this patchset and take action on them? Thank you!
> >
> > Who maintains this? I don't actually know, it's not powerpc code, or is it?
>
> Yes, it's not powerpc code, it is irqchip code, maintained by Thomas, Jason and Marc according to MAINTAINERS file.
>
> Hi Thomas, Jason and Marc,
>
> Could you keep an eye on this patchset? Thank you!
It's on my radar, but I have zero capacity at the moment. Hopefully Marc
can spare a few cycles.
Thanks,
tglx
^ permalink raw reply [flat|nested] 16+ messages in thread
* RE: [PATCH v10 0/4] this patchset is to remove PPCisms for QEIC
2017-11-01 17:09 ` Thomas Gleixner
@ 2017-11-02 1:41 ` Qiang Zhao
2017-11-02 10:12 ` Marc Zyngier
1 sibling, 0 replies; 16+ messages in thread
From: Qiang Zhao @ 2017-11-02 1:41 UTC (permalink / raw)
To: Thomas Gleixner
Cc: Michael Ellerman, Jason Cooper, Marc Zyngier, oss@buserror.net,
linuxppc-dev@lists.ozlabs.org, Xiaobo Xie,
linux-kernel@vger.kernel.org
On Wed, 1 Nov 2017, Thomas Gleixner <tglx@linutronix.de> wrote:
> -----Original Message-----
> From: Thomas Gleixner [mailto:tglx@linutronix.de]
> Sent: Thursday, November 02, 2017 1:10 AM
> To: Qiang Zhao <qiang.zhao@nxp.com>
> Cc: Michael Ellerman <mpe@ellerman.id.au>; Jason Cooper
> <jason@lakedaemon.net>; Marc Zyngier <marc.zyngier@arm.com>;
> oss@buserror.net; linuxppc-dev@lists.ozlabs.org; Xiaobo Xie
> <xiaobo.xie@nxp.com>; linux-kernel@vger.kernel.org
> Subject: RE: [PATCH v10 0/4] this patchset is to remove PPCisms for QEIC
>=20
> On Wed, 1 Nov 2017, Qiang Zhao wrote:
> > Michael Ellerman <mpe@ellerman.id.au> wrote
> > >
> > > Qiang Zhao <qiang.zhao@nxp.com> writes:
> > >
> > > > Hi all,
> > > >
> > > > Could anybody review this patchset and take action on them? Thank y=
ou!
> > >
> > > Who maintains this? I don't actually know, it's not powerpc code, or =
is it?
> >
> > Yes, it's not powerpc code, it is irqchip code, maintained by Thomas, J=
ason and
> Marc according to MAINTAINERS file.
> >
> > Hi Thomas, Jason and Marc,
> >
> > Could you keep an eye on this patchset? Thank you!
>=20
> It's on my radar, but I have zero capacity at the moment. Hopefully Marc =
can
> spare a few cycles.
>=20
> Thanks,
>=20
> tglx
Thank you!
Best Regards
Qiang Zhao
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v10 0/4] this patchset is to remove PPCisms for QEIC
2017-11-01 17:09 ` Thomas Gleixner
2017-11-02 1:41 ` Qiang Zhao
@ 2017-11-02 10:12 ` Marc Zyngier
1 sibling, 0 replies; 16+ messages in thread
From: Marc Zyngier @ 2017-11-02 10:12 UTC (permalink / raw)
To: Thomas Gleixner, Qiang Zhao
Cc: Michael Ellerman, Jason Cooper, oss@buserror.net,
linuxppc-dev@lists.ozlabs.org, Xiaobo Xie,
linux-kernel@vger.kernel.org
On 01/11/17 17:09, Thomas Gleixner wrote:
> On Wed, 1 Nov 2017, Qiang Zhao wrote:
>> Michael Ellerman <mpe@ellerman.id.au> wrote
>>>
>>> Qiang Zhao <qiang.zhao@nxp.com> writes:
>>>
>>>> Hi all,
>>>>
>>>> Could anybody review this patchset and take action on them? Thank you!
>>>
>>> Who maintains this? I don't actually know, it's not powerpc code, or is it?
>>
>> Yes, it's not powerpc code, it is irqchip code, maintained by Thomas, Jason and Marc according to MAINTAINERS file.
>>
>> Hi Thomas, Jason and Marc,
>>
>> Could you keep an eye on this patchset? Thank you!
>
> It's on my radar, but I have zero capacity at the moment. Hopefully Marc
> can spare a few cycles.
I'll try, but I haven't been cc-ed on that one. I'll try to dig it out.
Thanks,
M.
--
Jazz is not dead. It just smells funny...
^ permalink raw reply [flat|nested] 16+ messages in thread