From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from gate.crashing.org (gate.crashing.org [63.228.1.57]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3xbhVm4Cx8zDqVg for ; Tue, 22 Aug 2017 04:07:44 +1000 (AEST) Message-ID: <1503334155.2195.17.camel@kernel.crashing.org> Subject: Re: [v3,3/3] powerpc/mm/cxl: Add the fault handling cpu to mm cpumask From: Benjamin Herrenschmidt To: Michael Ellerman , "Aneesh Kumar K.V" , paulus@samba.org Cc: linuxppc-dev@lists.ozlabs.org Date: Mon, 21 Aug 2017 09:49:15 -0700 In-Reply-To: <3xbZXv0yxCz9t0F@ozlabs.org> References: <3xbZXv0yxCz9t0F@ozlabs.org> Content-Type: text/plain; charset="UTF-8" Mime-Version: 1.0 List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , On Mon, 2017-08-21 at 23:39 +1000, Michael Ellerman wrote: > On Thu, 2017-07-27 at 06:24:55 UTC, "Aneesh Kumar K.V" wrote: > > We use mm cpumask for serializing against lockless page table walk. Anybody > > who is doing a lockless page table walk is expected to disable irq and only > > cpus in mm cpumask is expected do the lockless walk. This ensure that > > a THP split can send IPI to only cpus in the mm cpumask, to make sure there > > are no parallel lockless page table walk. > > > > Add the CAPI fault handling cpu to the mm cpumask so that we can do the lockless > > page table walk while inserting hash page table entries. > > > > Reviewed-by: Frederic Barrat > > Signed-off-by: Aneesh Kumar K.V > > Applied to powerpc next, thanks. > > https://git.kernel.org/powerpc/c/0f4bc0932e51817105fdee77a46680 Do you need barriers between the cpumask set and the walking ? Cheers, Ben.