From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pf0-x242.google.com (mail-pf0-x242.google.com [IPv6:2607:f8b0:400e:c00::242]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3zrQsP1FRdzDqKx for ; Wed, 28 Feb 2018 04:38:33 +1100 (AEDT) Received: by mail-pf0-x242.google.com with SMTP id q13so8238939pff.0 for ; Tue, 27 Feb 2018 09:38:33 -0800 (PST) From: wei.guo.simon@gmail.com To: linuxppc-dev@lists.ozlabs.org Cc: Paul Mackerras , kvm@vger.kernel.org, kvm-ppc@vger.kernel.org, Simon Guo Subject: [PATCH v2 06/30] KVM: PPC: Book3S PR: turn on FP/VSX/VMX MSR bits in kvmppc_save_tm() Date: Wed, 28 Feb 2018 01:37:13 +0800 Message-Id: <1519753057-11059-7-git-send-email-wei.guo.simon@gmail.com> In-Reply-To: <1519753057-11059-1-git-send-email-wei.guo.simon@gmail.com> References: <1519753057-11059-1-git-send-email-wei.guo.simon@gmail.com> List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , From: Simon Guo kvmppc_save_tm() invokes store_fp_state/store_vr_state(). So it is mandatory to turn on FP/VSX/VMX MSR bits for its execution, just like what kvmppc_restore_tm() did. Previsouly HV KVM has turned the bits on outside of function kvmppc_save_tm(). Now we include this bit change in kvmppc_save_tm() so that the logic is more clean. And PR KVM can reuse it later. Signed-off-by: Simon Guo Reviewed-by: Paul Mackerras --- arch/powerpc/kvm/tm.S | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/powerpc/kvm/tm.S b/arch/powerpc/kvm/tm.S index e779b15..2d6fe5b 100644 --- a/arch/powerpc/kvm/tm.S +++ b/arch/powerpc/kvm/tm.S @@ -43,6 +43,8 @@ _GLOBAL(kvmppc_save_tm) mfmsr r8 li r0, 1 rldimi r8, r0, MSR_TM_LG, 63-MSR_TM_LG + ori r8, r8, MSR_FP + oris r8, r8, (MSR_VEC | MSR_VSX)@h mtmsrd r8 rldicl. r4, r4, 64 - MSR_TS_S_LG, 62 -- 1.8.3.1