From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from gate.crashing.org (gate.crashing.org [63.228.1.57]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 409zFR1cQTzF2Dl for ; Wed, 28 Mar 2018 17:56:42 +1100 (AEDT) Message-ID: <1522220165.7364.110.camel@kernel.crashing.org> Subject: Re: RFC on writel and writel_relaxed From: Benjamin Herrenschmidt To: Linus Torvalds Cc: Alexander Duyck , Will Deacon , Sinan Kaya , Arnd Bergmann , Jason Gunthorpe , David Laight , Oliver , "open list:LINUX FOR POWERPC (32-BIT AND 64-BIT)" , "linux-rdma@vger.kernel.org" , "Paul E. McKenney" , "netdev@vger.kernel.org" Date: Wed, 28 Mar 2018 17:56:05 +1100 In-Reply-To: References: <1521854626.16434.359.camel@kernel.crashing.org> <58ce5b83f40f4775bec1be8db66adb0d@AcuMS.aculab.com> <20180326165425.GA15554@ziepe.ca> <20180326202545.GB15554@ziepe.ca> <20180326210951.GD15554@ziepe.ca> <1522101616.7364.13.camel@kernel.crashing.org> <1e077f6a-90b6-cce9-6f0f-a8c003fec850@codeaurora.org> <20180327151029.GB17494@arm.com> <1522186396.7364.61.camel@kernel.crashing.org> <1522198981.7364.81.camel@kernel.crashing.org> <1522211620.7364.94.camel@kernel.crashing.org> <1522219376.7364.109.camel@kernel.crashing.org> Content-Type: text/plain; charset="UTF-8" Mime-Version: 1.0 List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , On Wed, 2018-03-28 at 06:53 +0000, Linus Torvalds wrote: > > > On Tue, Mar 27, 2018, 20:43 Benjamin Herrenschmidt ing.org> wrote: > > > > > > Of course, you'd have to be pretty odd to want to start a DMA > > with a > > > read anyway - partly exactly because it's bad for performance > > since > > > reads will be synchronous and not buffered like a write). > > > > I have bad memories of old adaptec controllers ... > > *Old* adaptec controllers were likely to use the in/out instructions > for status and command data. > > Those are actually even more ordered than UC reads and writes: the > in/out instructions are not just fully ordered, but are fully > *synchronous* on x86. > > So not just doing accesses in order, but actually waiting for > everything to drain before they start executing, but they also wait > for the operation itself to complete (ie "out" will not just queue > the write, it will then wait for the queue to empty and the write > data to hit the line). > > That's why in/out were *so* slow, and why nobody uses them any more > (well, the address size limitations and the lack of any remapping of > the address obviously also are a reason). All true indeed, though a lot of other archs never quite made them fully synchronous, which was another can of worms ... oh well. As for Adaptec, you might be right, I do remember having cases of old stuff triggering DMA on reads, it might have been "Mac" variants of Adaptec using MMIO or something... Cheers, Ben.