From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from gate.crashing.org (gate.crashing.org [63.228.1.57]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 40B3G73nCGzF2L0 for ; Wed, 28 Mar 2018 20:57:35 +1100 (AEDT) Message-ID: <1522231010.21446.8.camel@kernel.crashing.org> Subject: Re: RFC on writel and writel_relaxed From: Benjamin Herrenschmidt To: Will Deacon , David Laight Cc: Sinan Kaya , Arnd Bergmann , Jason Gunthorpe , Oliver , "open list:LINUX FOR POWERPC (32-BIT AND 64-BIT)" , "linux-rdma@vger.kernel.org" , "Paul E. McKenney" , Peter Zijlstra , Ingo Molnar , Jonathan Corbet Date: Wed, 28 Mar 2018 20:56:50 +1100 In-Reply-To: <20180328090907.GC28871@arm.com> References: <20180327095745.GB29373@arm.com> <20180327100944.GD29373@arm.com> <20180327110258.GF2464@arm.com> <20180327143628.GA10642@arm.com> <1522186185.7364.59.camel@kernel.crashing.org> <20180328085338.GA28871@arm.com> <5d3973edea93473197505f2e42cd3107@AcuMS.aculab.com> <20180328090907.GC28871@arm.com> Content-Type: text/plain; charset="UTF-8" Mime-Version: 1.0 List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , On Wed, 2018-03-28 at 10:09 +0100, Will Deacon wrote: > On Wed, Mar 28, 2018 at 09:00:01AM +0000, David Laight wrote: > > From: Will Deacon > > > Sent: 28 March 2018 09:54 > > > > ... > > > > > I don't think so. My reading of memory-barriers.txt says that writeX might > > > > > expand to outX, and outX is not ordered with respect to other types of > > > > > memory. > > > > > > > > Ugh ? > > > > > > > > My understanding of HW at least is the exact opposite. outX is *more* > > > > ordered if anything, than any other accessors. IO space is completely > > > > synchronous, non posted and ordered afaik. > > > > > > I'm just going by memory-barriers.txt: > > > > > > > > > (*) inX(), outX(): > > > > > > [...] > > > > > > They are guaranteed to be fully ordered with respect to each other. > > > > > > They are not guaranteed to be fully ordered with respect to other types of > > > memory and I/O operation. > > > > A long time ago there was a document from Intel that said that inb/outb weren't > > necessarily synchronised wrt memory accesses. > > (Might be P-pro era). > > However no processors actually behaved that way and more recent docs > > say that inb/outb are fully ordered. > > Thank you, David! I'll write another patch fixing this up and hopefully > we'll soon have one making writeX/readX much clearer. Thanks for doing the grunt work Will ! :-) Cheers, Ben.