* [PATCH] powerpc/dts/fsl: t2080rdb: reorder the Cortina PHY XFI lanes
@ 2018-09-20 11:47 Camelia Groza
0 siblings, 0 replies; only message in thread
From: Camelia Groza @ 2018-09-20 11:47 UTC (permalink / raw)
To: oss, robh+dt, mark.rutland
Cc: benh, paulus, mpe, devicetree, linuxppc-dev, linux-kernel,
Camelia Groza
According to the T2080RDB schematics, for the CS4315 PHY, the XFI 1 lane is
connected to SFP 2 and the XFI 2 lane is connected to SFP 1. Change the
device tree to reflect the correct PHY order and port association.
Signed-off-by: Camelia Groza <camelia.groza@nxp.com>
---
arch/powerpc/boot/dts/fsl/t2080rdb.dts | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/boot/dts/fsl/t2080rdb.dts b/arch/powerpc/boot/dts/fsl/t2080rdb.dts
index 55c0210..092a400 100644
--- a/arch/powerpc/boot/dts/fsl/t2080rdb.dts
+++ b/arch/powerpc/boot/dts/fsl/t2080rdb.dts
@@ -77,12 +77,12 @@
};
ethernet@f0000 {
- phy-handle = <&xg_cs4315_phy1>;
+ phy-handle = <&xg_cs4315_phy2>;
phy-connection-type = "xgmii";
};
ethernet@f2000 {
- phy-handle = <&xg_cs4315_phy2>;
+ phy-handle = <&xg_cs4315_phy1>;
phy-connection-type = "xgmii";
};
--
1.9.1
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2018-09-20 11:47 [PATCH] powerpc/dts/fsl: t2080rdb: reorder the Cortina PHY XFI lanes Camelia Groza
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