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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Fri, 15 Mar 2019 13:16:50 -0000 Received: from d06av25.portsmouth.uk.ibm.com (d06av25.portsmouth.uk.ibm.com [9.149.105.61]) by b06cxnps4076.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x2FDGn7M30015550 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 15 Mar 2019 13:16:49 GMT Received: from d06av25.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id A49F411C054; Fri, 15 Mar 2019 13:16:49 +0000 (GMT) Received: from d06av25.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 4DECA11C064; Fri, 15 Mar 2019 13:16:49 +0000 (GMT) Received: from localhost (unknown [9.78.193.169]) by d06av25.portsmouth.uk.ibm.com (Postfix) with ESMTP; Fri, 15 Mar 2019 13:16:49 +0000 (GMT) Date: Fri, 15 Mar 2019 18:46:45 +0530 From: "Naveen N. Rao" Subject: Re: bpf jit PPC64 (BE) test_verifier PTR_TO_STACK store/load failure To: Segher Boessenkool , Yauheni Kaliuta References: <20190313221436.GO3969@gate.crashing.org> In-Reply-To: <20190313221436.GO3969@gate.crashing.org> User-Agent: astroid/0.14.0 (https://github.com/astroidmail/astroid) MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 x-cbid: 19031513-4275-0000-0000-0000031B6412 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19031513-4276-0000-0000-00003829D9E0 Message-Id: <1552655762.yswcan0ziz.naveen@linux.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-03-15_09:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=0 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=689 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1903150094 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Daniel Borkmann , netdev@vger.kernel.org, Jiri Olsa , Sandipan Das , bpf@vger.kernel.org, linuxppc-dev@lists.ozlabs.org Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" Segher Boessenkool wrote: > Hi! >=20 > On Wed, Mar 13, 2019 at 12:54:16PM +0200, Yauheni Kaliuta wrote: >> This is because of the handling of the +2 offset. >=20 > The low two bits of instructions with primary opcodes 58 and 62 are part > of the opcode, not the offset. These instructions can not have offsets > with the low two bits non-zero. >=20 >> For stores it is: >> #define PPC_STD(r, base, i) EMIT(PPC_INST_STD | ___PPC_RS(r) | \ >> ___PPC_RA(base) | ((i) & 0xfffc)) >>=20 >> and for loads >> #define PPC_LD(r, base, i) EMIT(PPC_INST_LD | ___PPC_RT(r) | \ >> ___PPC_RA(base) | IMM_L(i)) >> #define IMM_L(i) ((uintptr_t)(i) & 0xffff) >>=20 >> So, in the load case the offset +2 (immediate value) is not >> masked and turns the instruction to lwa instead of ld. >>=20 >> Would it be correct to & 0xfffc the immediate value as well? >=20 > That is only part of it. The other thing is you have to make sure those > low bits are zero *already* (and then you do not need the mask anymore). > For example, if the low two bits are not zero load the offset into a > register instead (and then do ldx or lwax). Thanks for pointing that out, Segher. That is a detail that is easily=20 missed. - Naveen =