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Thu, 11 Jul 2019 18:03:02 -0700 (PDT) Received: from localhost ([220.240.228.224]) by smtp.gmail.com with ESMTPSA id u23sm7183631pfn.140.2019.07.11.18.03.01 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Thu, 11 Jul 2019 18:03:01 -0700 (PDT) Date: Fri, 12 Jul 2019 10:59:54 +1000 From: Nicholas Piggin Subject: Re: [PATCH v4 1/8] KVM: PPC: Ultravisor: Introduce the MSR_S bit To: Claudio Carvalho , linuxppc-dev@ozlabs.org, Michael Ellerman References: <20190628200825.31049-1-cclaudio@linux.ibm.com> <20190628200825.31049-2-cclaudio@linux.ibm.com> <87muhkg258.fsf@concordia.ellerman.id.au> In-Reply-To: <87muhkg258.fsf@concordia.ellerman.id.au> MIME-Version: 1.0 User-Agent: astroid/0.14.0 (https://github.com/astroidmail/astroid) Message-Id: <1562893118.ys3k642fnf.astroid@bobo.none> Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Madhavan Srinivasan , Michael Anderson , Ram Pai , kvm-ppc@vger.kernel.org, Bharata B Rao , Ryan Grimm , Sukadev Bhattiprolu , Thiago Bauermann , Anshuman Khandual Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" Michael Ellerman's on July 11, 2019 10:57 pm: > Claudio Carvalho writes: >> From: Sukadev Bhattiprolu >> >> The ultravisor processor mode is introduced in POWER platforms that >> supports the Protected Execution Facility (PEF). Ultravisor is higher >> privileged than hypervisor mode. >> >> In PEF enabled platforms, the MSR_S bit is used to indicate if the >> thread is in secure state. With the MSR_S bit, the privilege state of >> the thread is now determined by MSR_S, MSR_HV and MSR_PR, as follows: >> >> S HV PR >> ----------------------- >> 0 x 1 problem >> 1 0 1 problem >> x x 0 privileged >> x 1 0 hypervisor >> 1 1 0 ultravisor >> 1 1 1 reserved >=20 > What are you trying to express with the 'x' value? >=20 > I guess you mean it as "either" or "don't care" - but then you have > cases where it could only have one value, such as hypervisor. I think it > would be clearer if you spelled it out more explicitly. >=20 >> The hypervisor doesn't (and can't) run with the MSR_S bit set, but a >> secure guest and the ultravisor firmware do. >=20 > I know you're trying to be helpful, but this comment is really just > confusing to someone who doesn't have all the documentation. >=20 > I'd really like to see something in Documentation/powerpc describing at > least the outline of how the system works. I'm pretty sure most of that > is public, so even if it's mostly a list of references to other > documentations or presentations that would be fine. But I'm not really > happy with a whole new processor mode appearing with zero documentation > in the tree. >=20 >> Signed-off-by: Sukadev Bhattiprolu >> Signed-off-by: Ram Pai >> [ Update the commit message ] >=20 > It's normal to prefix these comments with your handle to make it clear > who is saying it. >=20 >> Signed-off-by: Claudio Carvalho >> --- >> arch/powerpc/include/asm/reg.h | 3 +++ >> 1 file changed, 3 insertions(+) >> >> diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/r= eg.h >> index 10caa145f98b..39b4c0a519f5 100644 >> --- a/arch/powerpc/include/asm/reg.h >> +++ b/arch/powerpc/include/asm/reg.h >> @@ -38,6 +38,7 @@ >> #define MSR_TM_LG 32 /* Trans Mem Available */ >> #define MSR_VEC_LG 25 /* Enable AltiVec */ >> #define MSR_VSX_LG 23 /* Enable VSX */ >> +#define MSR_S_LG 22 /* Secure VM bit */ >=20 > I don't think that's the best description, because it's also the > Ultravisor bit when MSR[HV] =3D 1. >=20 > So "Secure state" as you have below would be better IMO. Ooops I see Michael covered everything I wrote, sorry for the noise I missed the thread. Thanks, Nick =