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Thu, 11 Jul 2019 19:06:31 -0700 (PDT) Received: from localhost ([220.240.228.224]) by smtp.gmail.com with ESMTPSA id f12sm6336662pgo.85.2019.07.11.19.06.29 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Thu, 11 Jul 2019 19:06:30 -0700 (PDT) Date: Fri, 12 Jul 2019 12:03:21 +1000 From: Nicholas Piggin Subject: Re: [PATCH v4 7/8] KVM: PPC: Ultravisor: Enter a secure guest To: Claudio Carvalho , linuxppc-dev@ozlabs.org References: <20190628200825.31049-1-cclaudio@linux.ibm.com> <20190628200825.31049-8-cclaudio@linux.ibm.com> In-Reply-To: <20190628200825.31049-8-cclaudio@linux.ibm.com> MIME-Version: 1.0 User-Agent: astroid/0.14.0 (https://github.com/astroidmail/astroid) Message-Id: <1562896723.n2w6yyxx6b.astroid@bobo.none> Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Madhavan Srinivasan , Michael Anderson , Ram Pai , kvm-ppc@vger.kernel.org, Bharata B Rao , Ryan Grimm , Sukadev Bhattiprolu , Thiago Bauermann , Anshuman Khandual Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" Claudio Carvalho's on June 29, 2019 6:08 am: > From: Sukadev Bhattiprolu >=20 > To enter a secure guest, we have to go through the ultravisor, therefore > we do a ucall when we are entering a secure guest. >=20 > This change is needed for any sort of entry to the secure guest from the > hypervisor, whether it is a return from an hcall, a return from a > hypervisor interrupt, or the first time that a secure guest vCPU is run. >=20 > If we are returning from an hcall, the results are already in the > appropriate registers R3:12, except for R3, R6 and R7. R3 has the status > of the reflected hcall, therefore we move it to R0 for the ultravisor and > set R3 to the UV_RETURN ucall number. R6,7 were used as temporary > registers, hence we restore them. >=20 > Have fast_guest_return check the kvm_arch.secure_guest field so that a > new CPU enters UV when started (in response to a RTAS start-cpu call). >=20 > Thanks to input from Paul Mackerras, Ram Pai and Mike Anderson. >=20 > Signed-off-by: Sukadev Bhattiprolu > [ Pass SRR1 in r11 for UV_RETURN, fix kvmppc_msr_interrupt to preserve > the MSR_S bit ] > Signed-off-by: Paul Mackerras > [ Fix UV_RETURN ucall number and arch.secure_guest check ] > Signed-off-by: Ram Pai > [ Save the actual R3 in R0 for the ultravisor and use R3 for the > UV_RETURN ucall number. Update commit message and ret_to_ultra comment = ] > Signed-off-by: Claudio Carvalho > --- > arch/powerpc/include/asm/kvm_host.h | 1 + > arch/powerpc/include/asm/ultravisor-api.h | 1 + > arch/powerpc/kernel/asm-offsets.c | 1 + > arch/powerpc/kvm/book3s_hv_rmhandlers.S | 40 +++++++++++++++++++---- > 4 files changed, 37 insertions(+), 6 deletions(-) >=20 > diff --git a/arch/powerpc/include/asm/kvm_host.h b/arch/powerpc/include/a= sm/kvm_host.h > index 013c76a0a03e..184becb62ea4 100644 > --- a/arch/powerpc/include/asm/kvm_host.h > +++ b/arch/powerpc/include/asm/kvm_host.h > @@ -294,6 +294,7 @@ struct kvm_arch { > cpumask_t cpu_in_guest; > u8 radix; > u8 fwnmi_enabled; > + u8 secure_guest; > bool threads_indep; > bool nested_enable; > pgd_t *pgtable; > diff --git a/arch/powerpc/include/asm/ultravisor-api.h b/arch/powerpc/inc= lude/asm/ultravisor-api.h > index 141940771add..7c4d0b4ced12 100644 > --- a/arch/powerpc/include/asm/ultravisor-api.h > +++ b/arch/powerpc/include/asm/ultravisor-api.h > @@ -19,5 +19,6 @@ > =20 > /* opcodes */ > #define UV_WRITE_PATE 0xF104 > +#define UV_RETURN 0xF11C > =20 > #endif /* _ASM_POWERPC_ULTRAVISOR_API_H */ > diff --git a/arch/powerpc/kernel/asm-offsets.c b/arch/powerpc/kernel/asm-= offsets.c > index 8e02444e9d3d..44742724513e 100644 > --- a/arch/powerpc/kernel/asm-offsets.c > +++ b/arch/powerpc/kernel/asm-offsets.c > @@ -508,6 +508,7 @@ int main(void) > OFFSET(KVM_VRMA_SLB_V, kvm, arch.vrma_slb_v); > OFFSET(KVM_RADIX, kvm, arch.radix); > OFFSET(KVM_FWNMI, kvm, arch.fwnmi_enabled); > + OFFSET(KVM_SECURE_GUEST, kvm, arch.secure_guest); > OFFSET(VCPU_DSISR, kvm_vcpu, arch.shregs.dsisr); > OFFSET(VCPU_DAR, kvm_vcpu, arch.shregs.dar); > OFFSET(VCPU_VPA, kvm_vcpu, arch.vpa.pinned_addr); > diff --git a/arch/powerpc/kvm/book3s_hv_rmhandlers.S b/arch/powerpc/kvm/b= ook3s_hv_rmhandlers.S > index cffb365d9d02..89813ca987c2 100644 > --- a/arch/powerpc/kvm/book3s_hv_rmhandlers.S > +++ b/arch/powerpc/kvm/book3s_hv_rmhandlers.S > @@ -36,6 +36,7 @@ > #include > #include > #include > +#include > =20 > /* Sign-extend HDEC if not on POWER9 */ > #define EXTEND_HDEC(reg) \ > @@ -1092,16 +1093,12 @@ BEGIN_FTR_SECTION > END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR) > =20 > ld r5, VCPU_LR(r4) > - ld r6, VCPU_CR(r4) > mtlr r5 > - mtcr r6 > =20 > ld r1, VCPU_GPR(R1)(r4) > ld r2, VCPU_GPR(R2)(r4) > ld r3, VCPU_GPR(R3)(r4) > ld r5, VCPU_GPR(R5)(r4) > - ld r6, VCPU_GPR(R6)(r4) > - ld r7, VCPU_GPR(R7)(r4) > ld r8, VCPU_GPR(R8)(r4) > ld r9, VCPU_GPR(R9)(r4) > ld r10, VCPU_GPR(R10)(r4) Just to try to be less arbitrary about things, could you use regs adjacent to r4? Generally good because then it has a chance to get our loads paired up (which may not help some CPUs). Thanks, Nick =