* Re: [PATCH v2] powerpc: Allow flush_(inval_)dcache_range to work across ranges >4GB
2019-08-21 0:19 [PATCH v2] powerpc: Allow flush_(inval_)dcache_range to work across ranges >4GB Alastair D'Silva
@ 2019-08-26 16:50 ` Greg Kroah-Hartman
2019-08-26 20:08 ` Christophe Leroy
2019-08-27 1:50 ` Michael Ellerman
` (4 subsequent siblings)
5 siblings, 1 reply; 9+ messages in thread
From: Greg Kroah-Hartman @ 2019-08-26 16:50 UTC (permalink / raw)
To: Alastair D'Silva
Cc: alastair, linux-kernel, stable, Paul Mackerras, Thomas Gleixner,
linuxppc-dev, Allison Randal
On Wed, Aug 21, 2019 at 10:19:27AM +1000, Alastair D'Silva wrote:
> From: Alastair D'Silva <alastair@d-silva.org>
>
> The upstream commit:
> 22e9c88d486a ("powerpc/64: reuse PPC32 static inline flush_dcache_range()")
> has a similar effect, but since it is a rewrite of the assembler to C, is
> too invasive for stable. This patch is a minimal fix to address the issue in
> assembler.
>
> This patch applies cleanly to v5.2, v4.19 & v4.14.
>
> When calling flush_(inval_)dcache_range with a size >4GB, we were masking
> off the upper 32 bits, so we would incorrectly flush a range smaller
> than intended.
>
> This patch replaces the 32 bit shifts with 64 bit ones, so that
> the full size is accounted for.
>
> Changelog:
> v2
> - Add related upstream commit
>
> Signed-off-by: Alastair D'Silva <alastair@d-silva.org>
> ---
> arch/powerpc/kernel/misc_64.S | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/powerpc/kernel/misc_64.S b/arch/powerpc/kernel/misc_64.S
> index 1ad4089dd110..d4d096f80f4b 100644
> --- a/arch/powerpc/kernel/misc_64.S
> +++ b/arch/powerpc/kernel/misc_64.S
> @@ -130,7 +130,7 @@ _GLOBAL_TOC(flush_dcache_range)
> subf r8,r6,r4 /* compute length */
> add r8,r8,r5 /* ensure we get enough */
> lwz r9,DCACHEL1LOGBLOCKSIZE(r10) /* Get log-2 of dcache block size */
> - srw. r8,r8,r9 /* compute line count */
> + srd. r8,r8,r9 /* compute line count */
> beqlr /* nothing to do? */
> mtctr r8
> 0: dcbst 0,r6
> @@ -148,7 +148,7 @@ _GLOBAL(flush_inval_dcache_range)
> subf r8,r6,r4 /* compute length */
> add r8,r8,r5 /* ensure we get enough */
> lwz r9,DCACHEL1LOGBLOCKSIZE(r10)/* Get log-2 of dcache block size */
> - srw. r8,r8,r9 /* compute line count */
> + srd. r8,r8,r9 /* compute line count */
> beqlr /* nothing to do? */
> sync
> isync
I need an ack from the powerpc maintainer(s) before I can take this.
thanks,
greg k-h
^ permalink raw reply [flat|nested] 9+ messages in thread* Re: [PATCH v2] powerpc: Allow flush_(inval_)dcache_range to work across ranges >4GB
2019-08-26 16:50 ` Greg Kroah-Hartman
@ 2019-08-26 20:08 ` Christophe Leroy
2019-08-27 6:18 ` Greg Kroah-Hartman
0 siblings, 1 reply; 9+ messages in thread
From: Christophe Leroy @ 2019-08-26 20:08 UTC (permalink / raw)
To: Greg Kroah-Hartman, Alastair D'Silva
Cc: linux-kernel, stable, Paul Mackerras, alastair, Thomas Gleixner,
linuxppc-dev, Allison Randal
Le 26/08/2019 à 18:50, Greg Kroah-Hartman a écrit :
> On Wed, Aug 21, 2019 at 10:19:27AM +1000, Alastair D'Silva wrote:
>> From: Alastair D'Silva <alastair@d-silva.org>
>>
>> The upstream commit:
>> 22e9c88d486a ("powerpc/64: reuse PPC32 static inline flush_dcache_range()")
>> has a similar effect, but since it is a rewrite of the assembler to C, is
>> too invasive for stable. This patch is a minimal fix to address the issue in
>> assembler.
>>
>> This patch applies cleanly to v5.2, v4.19 & v4.14.
>>
>> When calling flush_(inval_)dcache_range with a size >4GB, we were masking
>> off the upper 32 bits, so we would incorrectly flush a range smaller
>> than intended.
>>
>> This patch replaces the 32 bit shifts with 64 bit ones, so that
>> the full size is accounted for.
>>
>> Changelog:
>> v2
>> - Add related upstream commit
>>
>> Signed-off-by: Alastair D'Silva <alastair@d-silva.org>
>> ---
>> arch/powerpc/kernel/misc_64.S | 4 ++--
>> 1 file changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/arch/powerpc/kernel/misc_64.S b/arch/powerpc/kernel/misc_64.S
>> index 1ad4089dd110..d4d096f80f4b 100644
>> --- a/arch/powerpc/kernel/misc_64.S
>> +++ b/arch/powerpc/kernel/misc_64.S
>> @@ -130,7 +130,7 @@ _GLOBAL_TOC(flush_dcache_range)
>> subf r8,r6,r4 /* compute length */
>> add r8,r8,r5 /* ensure we get enough */
>> lwz r9,DCACHEL1LOGBLOCKSIZE(r10) /* Get log-2 of dcache block size */
>> - srw. r8,r8,r9 /* compute line count */
>> + srd. r8,r8,r9 /* compute line count */
>> beqlr /* nothing to do? */
>> mtctr r8
>> 0: dcbst 0,r6
>> @@ -148,7 +148,7 @@ _GLOBAL(flush_inval_dcache_range)
>> subf r8,r6,r4 /* compute length */
>> add r8,r8,r5 /* ensure we get enough */
>> lwz r9,DCACHEL1LOGBLOCKSIZE(r10)/* Get log-2 of dcache block size */
>> - srw. r8,r8,r9 /* compute line count */
>> + srd. r8,r8,r9 /* compute line count */
>> beqlr /* nothing to do? */
>> sync
>> isync
>
> I need an ack from the powerpc maintainer(s) before I can take this.
I think you already got an ack (on v1). See
https://patchwork.ozlabs.org/patch/1147403/#2239663
Christophe
^ permalink raw reply [flat|nested] 9+ messages in thread* Re: [PATCH v2] powerpc: Allow flush_(inval_)dcache_range to work across ranges >4GB
2019-08-26 20:08 ` Christophe Leroy
@ 2019-08-27 6:18 ` Greg Kroah-Hartman
0 siblings, 0 replies; 9+ messages in thread
From: Greg Kroah-Hartman @ 2019-08-27 6:18 UTC (permalink / raw)
To: Christophe Leroy
Cc: Alastair D'Silva, linux-kernel, stable, Paul Mackerras,
alastair, Thomas Gleixner, linuxppc-dev, Allison Randal
On Mon, Aug 26, 2019 at 10:08:26PM +0200, Christophe Leroy wrote:
>
>
> Le 26/08/2019 à 18:50, Greg Kroah-Hartman a écrit :
> > On Wed, Aug 21, 2019 at 10:19:27AM +1000, Alastair D'Silva wrote:
> > > From: Alastair D'Silva <alastair@d-silva.org>
> > >
> > > The upstream commit:
> > > 22e9c88d486a ("powerpc/64: reuse PPC32 static inline flush_dcache_range()")
> > > has a similar effect, but since it is a rewrite of the assembler to C, is
> > > too invasive for stable. This patch is a minimal fix to address the issue in
> > > assembler.
> > >
> > > This patch applies cleanly to v5.2, v4.19 & v4.14.
> > >
> > > When calling flush_(inval_)dcache_range with a size >4GB, we were masking
> > > off the upper 32 bits, so we would incorrectly flush a range smaller
> > > than intended.
> > >
> > > This patch replaces the 32 bit shifts with 64 bit ones, so that
> > > the full size is accounted for.
> > >
> > > Changelog:
> > > v2
> > > - Add related upstream commit
> > >
> > > Signed-off-by: Alastair D'Silva <alastair@d-silva.org>
> > > ---
> > > arch/powerpc/kernel/misc_64.S | 4 ++--
> > > 1 file changed, 2 insertions(+), 2 deletions(-)
> > >
> > > diff --git a/arch/powerpc/kernel/misc_64.S b/arch/powerpc/kernel/misc_64.S
> > > index 1ad4089dd110..d4d096f80f4b 100644
> > > --- a/arch/powerpc/kernel/misc_64.S
> > > +++ b/arch/powerpc/kernel/misc_64.S
> > > @@ -130,7 +130,7 @@ _GLOBAL_TOC(flush_dcache_range)
> > > subf r8,r6,r4 /* compute length */
> > > add r8,r8,r5 /* ensure we get enough */
> > > lwz r9,DCACHEL1LOGBLOCKSIZE(r10) /* Get log-2 of dcache block size */
> > > - srw. r8,r8,r9 /* compute line count */
> > > + srd. r8,r8,r9 /* compute line count */
> > > beqlr /* nothing to do? */
> > > mtctr r8
> > > 0: dcbst 0,r6
> > > @@ -148,7 +148,7 @@ _GLOBAL(flush_inval_dcache_range)
> > > subf r8,r6,r4 /* compute length */
> > > add r8,r8,r5 /* ensure we get enough */
> > > lwz r9,DCACHEL1LOGBLOCKSIZE(r10)/* Get log-2 of dcache block size */
> > > - srw. r8,r8,r9 /* compute line count */
> > > + srd. r8,r8,r9 /* compute line count */
> > > beqlr /* nothing to do? */
> > > sync
> > > isync
> >
> > I need an ack from the powerpc maintainer(s) before I can take this.
>
> I think you already got an ack (on v1). See
> https://patchwork.ozlabs.org/patch/1147403/#2239663
How am I supposed to remember that? :)
greg k-h
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v2] powerpc: Allow flush_(inval_)dcache_range to work across ranges >4GB
2019-08-21 0:19 [PATCH v2] powerpc: Allow flush_(inval_)dcache_range to work across ranges >4GB Alastair D'Silva
2019-08-26 16:50 ` Greg Kroah-Hartman
@ 2019-08-27 1:50 ` Michael Ellerman
2019-08-27 6:19 ` Patch "powerpc: Allow flush_(inval_)dcache_range to work across ranges >4GB" has been added to the 4.14-stable tree gregkh
` (3 subsequent siblings)
5 siblings, 0 replies; 9+ messages in thread
From: Michael Ellerman @ 2019-08-27 1:50 UTC (permalink / raw)
To: Alastair D'Silva, alastair
Cc: linux-kernel, stable, Paul Mackerras, Greg Kroah-Hartman,
Thomas Gleixner, linuxppc-dev, Allison Randal
"Alastair D'Silva" <alastair@au1.ibm.com> writes:
> From: Alastair D'Silva <alastair@d-silva.org>
>
> The upstream commit:
> 22e9c88d486a ("powerpc/64: reuse PPC32 static inline flush_dcache_range()")
> has a similar effect, but since it is a rewrite of the assembler to C, is
> too invasive for stable. This patch is a minimal fix to address the issue in
> assembler.
>
> This patch applies cleanly to v5.2, v4.19 & v4.14.
>
> When calling flush_(inval_)dcache_range with a size >4GB, we were masking
> off the upper 32 bits, so we would incorrectly flush a range smaller
> than intended.
>
> This patch replaces the 32 bit shifts with 64 bit ones, so that
> the full size is accounted for.
>
> Changelog:
> v2
> - Add related upstream commit
>
> Signed-off-by: Alastair D'Silva <alastair@d-silva.org>
> ---
> arch/powerpc/kernel/misc_64.S | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
Acked-by: Michael Ellerman <mpe@ellerman.id.au>
cheers
> diff --git a/arch/powerpc/kernel/misc_64.S b/arch/powerpc/kernel/misc_64.S
> index 1ad4089dd110..d4d096f80f4b 100644
> --- a/arch/powerpc/kernel/misc_64.S
> +++ b/arch/powerpc/kernel/misc_64.S
> @@ -130,7 +130,7 @@ _GLOBAL_TOC(flush_dcache_range)
> subf r8,r6,r4 /* compute length */
> add r8,r8,r5 /* ensure we get enough */
> lwz r9,DCACHEL1LOGBLOCKSIZE(r10) /* Get log-2 of dcache block size */
> - srw. r8,r8,r9 /* compute line count */
> + srd. r8,r8,r9 /* compute line count */
> beqlr /* nothing to do? */
> mtctr r8
> 0: dcbst 0,r6
> @@ -148,7 +148,7 @@ _GLOBAL(flush_inval_dcache_range)
> subf r8,r6,r4 /* compute length */
> add r8,r8,r5 /* ensure we get enough */
> lwz r9,DCACHEL1LOGBLOCKSIZE(r10)/* Get log-2 of dcache block size */
> - srw. r8,r8,r9 /* compute line count */
> + srd. r8,r8,r9 /* compute line count */
> beqlr /* nothing to do? */
> sync
> isync
> --
> 2.21.0
^ permalink raw reply [flat|nested] 9+ messages in thread* Patch "powerpc: Allow flush_(inval_)dcache_range to work across ranges >4GB" has been added to the 4.14-stable tree
2019-08-21 0:19 [PATCH v2] powerpc: Allow flush_(inval_)dcache_range to work across ranges >4GB Alastair D'Silva
2019-08-26 16:50 ` Greg Kroah-Hartman
2019-08-27 1:50 ` Michael Ellerman
@ 2019-08-27 6:19 ` gregkh
2019-08-27 6:19 ` [PATCH v2] powerpc: Allow flush_(inval_)dcache_range to work across ranges >4GB Greg Kroah-Hartman
` (2 subsequent siblings)
5 siblings, 0 replies; 9+ messages in thread
From: gregkh @ 2019-08-27 6:19 UTC (permalink / raw)
To: alastair, alastair, allison, benh, gregkh, linuxppc-dev, mpe,
paulus, tglx
Cc: stable-commits
This is a note to let you know that I've just added the patch titled
powerpc: Allow flush_(inval_)dcache_range to work across ranges >4GB
to the 4.14-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
powerpc-allow-flush_-inval_-dcache_range-to-work-across-ranges-4gb.patch
and it can be found in the queue-4.14 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@vger.kernel.org> know about it.
From alastair@au1.ibm.com Tue Aug 27 08:18:42 2019
From: "Alastair D'Silva" <alastair@au1.ibm.com>
Date: Wed, 21 Aug 2019 10:19:27 +1000
Subject: powerpc: Allow flush_(inval_)dcache_range to work across ranges >4GB
To: alastair@d-silva.org
Cc: stable@vger.kernel.org, Benjamin Herrenschmidt <benh@kernel.crashing.org>, Paul Mackerras <paulus@samba.org>, Michael Ellerman <mpe@ellerman.id.au>, Thomas Gleixner <tglx@linutronix.de>, Greg Kroah-Hartman <gregkh@linuxfoundation.org>, Allison Randal <allison@lohutok.net>, linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org
Message-ID: <20190821001929.4253-1-alastair@au1.ibm.com>
From: Alastair D'Silva <alastair@d-silva.org>
The upstream commit:
22e9c88d486a ("powerpc/64: reuse PPC32 static inline flush_dcache_range()")
has a similar effect, but since it is a rewrite of the assembler to C, is
too invasive for stable. This patch is a minimal fix to address the issue in
assembler.
This patch applies cleanly to v5.2, v4.19 & v4.14.
When calling flush_(inval_)dcache_range with a size >4GB, we were masking
off the upper 32 bits, so we would incorrectly flush a range smaller
than intended.
This patch replaces the 32 bit shifts with 64 bit ones, so that
the full size is accounted for.
Signed-off-by: Alastair D'Silva <alastair@d-silva.org>
Acked-by: Michael Ellerman <mpe@ellerman.id.au>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
arch/powerpc/kernel/misc_64.S | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
--- a/arch/powerpc/kernel/misc_64.S
+++ b/arch/powerpc/kernel/misc_64.S
@@ -134,7 +134,7 @@ _GLOBAL_TOC(flush_dcache_range)
subf r8,r6,r4 /* compute length */
add r8,r8,r5 /* ensure we get enough */
lwz r9,DCACHEL1LOGBLOCKSIZE(r10) /* Get log-2 of dcache block size */
- srw. r8,r8,r9 /* compute line count */
+ srd. r8,r8,r9 /* compute line count */
beqlr /* nothing to do? */
mtctr r8
0: dcbst 0,r6
@@ -190,7 +190,7 @@ _GLOBAL(flush_inval_dcache_range)
subf r8,r6,r4 /* compute length */
add r8,r8,r5 /* ensure we get enough */
lwz r9,DCACHEL1LOGBLOCKSIZE(r10)/* Get log-2 of dcache block size */
- srw. r8,r8,r9 /* compute line count */
+ srd. r8,r8,r9 /* compute line count */
beqlr /* nothing to do? */
sync
isync
Patches currently in stable-queue which might be from alastair@au1.ibm.com are
queue-4.14/powerpc-allow-flush_-inval_-dcache_range-to-work-across-ranges-4gb.patch
^ permalink raw reply [flat|nested] 9+ messages in thread* Re: [PATCH v2] powerpc: Allow flush_(inval_)dcache_range to work across ranges >4GB
2019-08-21 0:19 [PATCH v2] powerpc: Allow flush_(inval_)dcache_range to work across ranges >4GB Alastair D'Silva
` (2 preceding siblings ...)
2019-08-27 6:19 ` Patch "powerpc: Allow flush_(inval_)dcache_range to work across ranges >4GB" has been added to the 4.14-stable tree gregkh
@ 2019-08-27 6:19 ` Greg Kroah-Hartman
2019-08-27 6:19 ` Patch "powerpc: Allow flush_(inval_)dcache_range to work across ranges >4GB" has been added to the 4.19-stable tree gregkh
2019-08-27 6:20 ` Patch "powerpc: Allow flush_(inval_)dcache_range to work across ranges >4GB" has been added to the 5.2-stable tree gregkh
5 siblings, 0 replies; 9+ messages in thread
From: Greg Kroah-Hartman @ 2019-08-27 6:19 UTC (permalink / raw)
To: Alastair D'Silva
Cc: alastair, linux-kernel, stable, Paul Mackerras, Thomas Gleixner,
linuxppc-dev, Allison Randal
On Wed, Aug 21, 2019 at 10:19:27AM +1000, Alastair D'Silva wrote:
> From: Alastair D'Silva <alastair@d-silva.org>
>
> The upstream commit:
> 22e9c88d486a ("powerpc/64: reuse PPC32 static inline flush_dcache_range()")
> has a similar effect, but since it is a rewrite of the assembler to C, is
> too invasive for stable. This patch is a minimal fix to address the issue in
> assembler.
>
> This patch applies cleanly to v5.2, v4.19 & v4.14.
>
> When calling flush_(inval_)dcache_range with a size >4GB, we were masking
> off the upper 32 bits, so we would incorrectly flush a range smaller
> than intended.
>
> This patch replaces the 32 bit shifts with 64 bit ones, so that
> the full size is accounted for.
>
> Changelog:
> v2
> - Add related upstream commit
Now applied, thanks.
greg k-h
^ permalink raw reply [flat|nested] 9+ messages in thread* Patch "powerpc: Allow flush_(inval_)dcache_range to work across ranges >4GB" has been added to the 4.19-stable tree
2019-08-21 0:19 [PATCH v2] powerpc: Allow flush_(inval_)dcache_range to work across ranges >4GB Alastair D'Silva
` (3 preceding siblings ...)
2019-08-27 6:19 ` [PATCH v2] powerpc: Allow flush_(inval_)dcache_range to work across ranges >4GB Greg Kroah-Hartman
@ 2019-08-27 6:19 ` gregkh
2019-08-27 6:20 ` Patch "powerpc: Allow flush_(inval_)dcache_range to work across ranges >4GB" has been added to the 5.2-stable tree gregkh
5 siblings, 0 replies; 9+ messages in thread
From: gregkh @ 2019-08-27 6:19 UTC (permalink / raw)
To: alastair, alastair, allison, benh, gregkh, linuxppc-dev, mpe,
paulus, tglx
Cc: stable-commits
This is a note to let you know that I've just added the patch titled
powerpc: Allow flush_(inval_)dcache_range to work across ranges >4GB
to the 4.19-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
powerpc-allow-flush_-inval_-dcache_range-to-work-across-ranges-4gb.patch
and it can be found in the queue-4.19 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@vger.kernel.org> know about it.
From alastair@au1.ibm.com Tue Aug 27 08:18:42 2019
From: "Alastair D'Silva" <alastair@au1.ibm.com>
Date: Wed, 21 Aug 2019 10:19:27 +1000
Subject: powerpc: Allow flush_(inval_)dcache_range to work across ranges >4GB
To: alastair@d-silva.org
Cc: stable@vger.kernel.org, Benjamin Herrenschmidt <benh@kernel.crashing.org>, Paul Mackerras <paulus@samba.org>, Michael Ellerman <mpe@ellerman.id.au>, Thomas Gleixner <tglx@linutronix.de>, Greg Kroah-Hartman <gregkh@linuxfoundation.org>, Allison Randal <allison@lohutok.net>, linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org
Message-ID: <20190821001929.4253-1-alastair@au1.ibm.com>
From: Alastair D'Silva <alastair@d-silva.org>
The upstream commit:
22e9c88d486a ("powerpc/64: reuse PPC32 static inline flush_dcache_range()")
has a similar effect, but since it is a rewrite of the assembler to C, is
too invasive for stable. This patch is a minimal fix to address the issue in
assembler.
This patch applies cleanly to v5.2, v4.19 & v4.14.
When calling flush_(inval_)dcache_range with a size >4GB, we were masking
off the upper 32 bits, so we would incorrectly flush a range smaller
than intended.
This patch replaces the 32 bit shifts with 64 bit ones, so that
the full size is accounted for.
Signed-off-by: Alastair D'Silva <alastair@d-silva.org>
Acked-by: Michael Ellerman <mpe@ellerman.id.au>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
arch/powerpc/kernel/misc_64.S | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
--- a/arch/powerpc/kernel/misc_64.S
+++ b/arch/powerpc/kernel/misc_64.S
@@ -135,7 +135,7 @@ _GLOBAL_TOC(flush_dcache_range)
subf r8,r6,r4 /* compute length */
add r8,r8,r5 /* ensure we get enough */
lwz r9,DCACHEL1LOGBLOCKSIZE(r10) /* Get log-2 of dcache block size */
- srw. r8,r8,r9 /* compute line count */
+ srd. r8,r8,r9 /* compute line count */
beqlr /* nothing to do? */
mtctr r8
0: dcbst 0,r6
@@ -153,7 +153,7 @@ _GLOBAL(flush_inval_dcache_range)
subf r8,r6,r4 /* compute length */
add r8,r8,r5 /* ensure we get enough */
lwz r9,DCACHEL1LOGBLOCKSIZE(r10)/* Get log-2 of dcache block size */
- srw. r8,r8,r9 /* compute line count */
+ srd. r8,r8,r9 /* compute line count */
beqlr /* nothing to do? */
sync
isync
Patches currently in stable-queue which might be from alastair@au1.ibm.com are
queue-4.19/powerpc-allow-flush_-inval_-dcache_range-to-work-across-ranges-4gb.patch
^ permalink raw reply [flat|nested] 9+ messages in thread* Patch "powerpc: Allow flush_(inval_)dcache_range to work across ranges >4GB" has been added to the 5.2-stable tree
2019-08-21 0:19 [PATCH v2] powerpc: Allow flush_(inval_)dcache_range to work across ranges >4GB Alastair D'Silva
` (4 preceding siblings ...)
2019-08-27 6:19 ` Patch "powerpc: Allow flush_(inval_)dcache_range to work across ranges >4GB" has been added to the 4.19-stable tree gregkh
@ 2019-08-27 6:20 ` gregkh
5 siblings, 0 replies; 9+ messages in thread
From: gregkh @ 2019-08-27 6:20 UTC (permalink / raw)
To: alastair, alastair, allison, benh, gregkh, linuxppc-dev, mpe,
paulus, tglx
Cc: stable-commits
This is a note to let you know that I've just added the patch titled
powerpc: Allow flush_(inval_)dcache_range to work across ranges >4GB
to the 5.2-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
powerpc-allow-flush_-inval_-dcache_range-to-work-across-ranges-4gb.patch
and it can be found in the queue-5.2 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@vger.kernel.org> know about it.
From alastair@au1.ibm.com Tue Aug 27 08:18:42 2019
From: "Alastair D'Silva" <alastair@au1.ibm.com>
Date: Wed, 21 Aug 2019 10:19:27 +1000
Subject: powerpc: Allow flush_(inval_)dcache_range to work across ranges >4GB
To: alastair@d-silva.org
Cc: stable@vger.kernel.org, Benjamin Herrenschmidt <benh@kernel.crashing.org>, Paul Mackerras <paulus@samba.org>, Michael Ellerman <mpe@ellerman.id.au>, Thomas Gleixner <tglx@linutronix.de>, Greg Kroah-Hartman <gregkh@linuxfoundation.org>, Allison Randal <allison@lohutok.net>, linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org
Message-ID: <20190821001929.4253-1-alastair@au1.ibm.com>
From: Alastair D'Silva <alastair@d-silva.org>
The upstream commit:
22e9c88d486a ("powerpc/64: reuse PPC32 static inline flush_dcache_range()")
has a similar effect, but since it is a rewrite of the assembler to C, is
too invasive for stable. This patch is a minimal fix to address the issue in
assembler.
This patch applies cleanly to v5.2, v4.19 & v4.14.
When calling flush_(inval_)dcache_range with a size >4GB, we were masking
off the upper 32 bits, so we would incorrectly flush a range smaller
than intended.
This patch replaces the 32 bit shifts with 64 bit ones, so that
the full size is accounted for.
Signed-off-by: Alastair D'Silva <alastair@d-silva.org>
Acked-by: Michael Ellerman <mpe@ellerman.id.au>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
arch/powerpc/kernel/misc_64.S | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
--- a/arch/powerpc/kernel/misc_64.S
+++ b/arch/powerpc/kernel/misc_64.S
@@ -130,7 +130,7 @@ _GLOBAL_TOC(flush_dcache_range)
subf r8,r6,r4 /* compute length */
add r8,r8,r5 /* ensure we get enough */
lwz r9,DCACHEL1LOGBLOCKSIZE(r10) /* Get log-2 of dcache block size */
- srw. r8,r8,r9 /* compute line count */
+ srd. r8,r8,r9 /* compute line count */
beqlr /* nothing to do? */
mtctr r8
0: dcbst 0,r6
@@ -148,7 +148,7 @@ _GLOBAL(flush_inval_dcache_range)
subf r8,r6,r4 /* compute length */
add r8,r8,r5 /* ensure we get enough */
lwz r9,DCACHEL1LOGBLOCKSIZE(r10)/* Get log-2 of dcache block size */
- srw. r8,r8,r9 /* compute line count */
+ srd. r8,r8,r9 /* compute line count */
beqlr /* nothing to do? */
sync
isync
Patches currently in stable-queue which might be from alastair@au1.ibm.com are
queue-5.2/powerpc-allow-flush_-inval_-dcache_range-to-work-across-ranges-4gb.patch
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