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[14.202.91.55]) by smtp.gmail.com with ESMTPSA id 131sm16437330pge.37.2019.08.27.05.49.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 27 Aug 2019 05:49:06 -0700 (PDT) Date: Tue, 27 Aug 2019 22:48:24 +1000 From: Nicholas Piggin Subject: Re: [PATCH 2/2] powerpc: cleanup hw_irq.h To: Benjamin Herrenschmidt , Christophe Leroy , Michael Ellerman , Paul Mackerras References: <0f7e164afb5d1b022441559fe5a999bb6d3c0a23.1566893505.git.christophe.leroy@c-s.fr> <81f39fa06ae582f4a783d26abd2b310204eba8f4.1566893505.git.christophe.leroy@c-s.fr> In-Reply-To: <81f39fa06ae582f4a783d26abd2b310204eba8f4.1566893505.git.christophe.leroy@c-s.fr> MIME-Version: 1.0 User-Agent: astroid/0.15.0 (https://github.com/astroidmail/astroid) Message-Id: <1566909844.x4jee1jjda.astroid@bobo.none> Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" Christophe Leroy's on August 27, 2019 6:13 pm: > SET_MSR_EE() is just use in this file and doesn't provide > any added value compared to mtmsr(). Drop it. >=20 > Add macros to use wrtee/wrteei insn. >=20 > Replace #ifdefs by IS_ENABLED() >=20 > Signed-off-by: Christophe Leroy > --- > arch/powerpc/include/asm/hw_irq.h | 57 ++++++++++++++++++---------------= ------ > arch/powerpc/include/asm/reg.h | 2 ++ > 2 files changed, 28 insertions(+), 31 deletions(-) >=20 > diff --git a/arch/powerpc/include/asm/hw_irq.h b/arch/powerpc/include/asm= /hw_irq.h > index 32a18f2f49bc..c25d57f25a8b 100644 > --- a/arch/powerpc/include/asm/hw_irq.h > +++ b/arch/powerpc/include/asm/hw_irq.h > @@ -226,8 +226,8 @@ static inline bool arch_irqs_disabled(void) > #endif /* CONFIG_PPC_BOOK3S */ > =20 > #ifdef CONFIG_PPC_BOOK3E > -#define __hard_irq_enable() asm volatile("wrteei 1" : : : "memory") > -#define __hard_irq_disable() asm volatile("wrteei 0" : : : "memory") > +#define __hard_irq_enable() wrteei(1) > +#define __hard_irq_disable() wrteei(0) > #else > #define __hard_irq_enable() __mtmsrd(MSR_EE|MSR_RI, 1) > #define __hard_irq_disable() __mtmsrd(MSR_RI, 1) > @@ -280,8 +280,6 @@ extern void force_external_irq_replay(void); > =20 > #else /* CONFIG_PPC64 */ > =20 > -#define SET_MSR_EE(x) mtmsr(x) > - > static inline unsigned long arch_local_save_flags(void) > { > return mfmsr(); > @@ -289,47 +287,44 @@ static inline unsigned long arch_local_save_flags(v= oid) > =20 > static inline void arch_local_irq_restore(unsigned long flags) > { > -#if defined(CONFIG_BOOKE) > - asm volatile("wrtee %0" : : "r" (flags) : "memory"); > -#else > - mtmsr(flags); > -#endif > + if (IS_ENABLED(CONFIG_BOOKE)) > + wrtee(flags); > + else > + mtmsr(flags); > } > =20 > static inline unsigned long arch_local_irq_save(void) > { > unsigned long flags =3D arch_local_save_flags(); > -#ifdef CONFIG_BOOKE > - asm volatile("wrteei 0" : : : "memory"); > -#elif defined(CONFIG_PPC_8xx) > - wrtspr(SPRN_EID); > -#else > - SET_MSR_EE(flags & ~MSR_EE); > -#endif > + > + if (IS_ENABLED(CONFIG_BOOKE)) > + wrteei(0); > + else if (IS_ENABLED(CONFIG_PPC_8xx)) > + wrtspr(SPRN_EID); > + else > + mtmsr(flags & ~MSR_EE); > + > return flags; > } > =20 > static inline void arch_local_irq_disable(void) > { > -#ifdef CONFIG_BOOKE > - asm volatile("wrteei 0" : : : "memory"); > -#elif defined(CONFIG_PPC_8xx) > - wrtspr(SPRN_EID); > -#else > - arch_local_irq_save(); > -#endif > + if (IS_ENABLED(CONFIG_BOOKE)) > + wrteei(0); > + else if (IS_ENABLED(CONFIG_PPC_8xx)) > + wrtspr(SPRN_EID); > + else > + mtmsr(mfmsr() & ~MSR_EE); > } > =20 > static inline void arch_local_irq_enable(void) > { > -#ifdef CONFIG_BOOKE > - asm volatile("wrteei 1" : : : "memory"); > -#elif defined(CONFIG_PPC_8xx) > - wrtspr(SPRN_EIE); > -#else > - unsigned long msr =3D mfmsr(); > - SET_MSR_EE(msr | MSR_EE); > -#endif > + if (IS_ENABLED(CONFIG_BOOKE)) > + wrteei(1); > + else if (IS_ENABLED(CONFIG_PPC_8xx)) > + wrtspr(SPRN_EIE); > + else > + mtmsr(mfmsr() | MSR_EE); > } > =20 > static inline bool arch_irqs_disabled_flags(unsigned long flags) > diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/re= g.h > index b17ee25df226..04896dd09455 100644 > --- a/arch/powerpc/include/asm/reg.h > +++ b/arch/powerpc/include/asm/reg.h > @@ -1361,6 +1361,8 @@ static inline void mtmsr_isync(unsigned long val) > #endif > #define wrtspr(rn) asm volatile("mtspr " __stringify(rn) ",0" : \ > : : "memory") > +#define wrtee(val) asm volatile("wrtee %0" : : "r" (val) : "memory") > +#define wrteei(val) asm volatile("wrteei %0" : : "i" (val) : "memory") Can you implement just one macro that uses __builtin_constant_p to=20 select between the imm and reg versions? I forgot if there's some corner cases that prevent that working with inline asm i constraints. Otherwise, looks like a nice cleanup. Thanks, Nick =