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Wed, 18 Dec 2019 23:13:04 +0000 (GMT) Received: from b03ledav003.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 5B76D6A04D; Wed, 18 Dec 2019 23:13:04 +0000 (GMT) Received: from [9.70.82.143] (unknown [9.70.82.143]) by b03ledav003.gho.boulder.ibm.com (Postfix) with ESMTP; Wed, 18 Dec 2019 23:13:04 +0000 (GMT) Subject: Re: [PATCH 04/14] powerpc/vas: Setup IRQ mapping and register port for each window From: Haren Myneni To: "Oliver O'Halloran" In-Reply-To: References: <1574816731.13250.9.camel@hbabu-laptop> Content-Type: text/plain; charset="UTF-8" Date: Wed, 18 Dec 2019 15:13:01 -0800 Message-ID: <1576710781.12797.10.camel@hbabu-laptop> Mime-Version: 1.0 X-Mailer: Evolution 2.28.3 Content-Transfer-Encoding: 7bit X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.95,18.0.572 definitions=2019-12-18_08:2019-12-17,2019-12-18 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 clxscore=1015 bulkscore=0 adultscore=0 suspectscore=2 mlxlogscore=999 malwarescore=0 mlxscore=0 phishscore=0 priorityscore=1501 impostorscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-1910280000 definitions=main-1912180172 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Device Tree , Michael Neuling , Herbert Xu , Nicholas Piggin , Sukadev Bhattiprolu , linuxppc-dev , Haren Myneni Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" On Wed, 2019-12-18 at 18:18 +1100, Oliver O'Halloran wrote: > On Wed, Nov 27, 2019 at 12:07 PM Haren Myneni wrote: > > > > *snip* > > > > @@ -36,7 +62,18 @@ static int init_vas_instance(struct platform_device *pdev) > > return -ENODEV; > > } > > > > - if (pdev->num_resources != 4) { > > + rc = of_property_read_u64(dn, "ibm,vas-port", &port); > > + if (rc) { > > + pr_err("No ibm,vas-port property for %s?\n", pdev->name); > > + /* No interrupts property */ > > + nresources = 4; > > + } > > + > > + /* > > + * interrupts property is available with 'ibm,vas-port' property. > > + * 4 Resources and 1 IRQ if interrupts property is available. > > + */ > > + if (pdev->num_resources != nresources) { > > pr_err("Unexpected DT configuration for [%s, %d]\n", > > pdev->name, vasid); > > return -ENODEV; > > Right, so adding the IRQ in firmware will break the VAS driver in > existing kernels since it changes the resource count. This is IMO a > bug in the VAS driver that you should fix, but it does mean we need to > think twice about having firmware assign an interrupt at boot. Correct, Hence added vas-user-space nvram switch in skiboot. > > I had a closer look at this series and I'm not convinced that any > firmware changes are actually required either. We already have OPAL > calls for allocating an hwirq for the kernel to use and for getting > the IRQ's XIVE trigger port (see pnv_ocxl_alloc_xive_irq() for an > example). Why not use those here too? Doing so would allow us to > assign interrupts to individual windows too which might be useful for > the windows used by the kernel. Thanks for the pointer. like using pnv_ocxl_alloc_xive_irq(), we can disregard FW change. BTW, VAS fault handling is needed only for user space VAS windows. int vas_alloc_xive_irq(u32 chipid, u32 *irq, u64 *trigger_addr) { __be64 flags, trigger_page; u32 hwirq; s64 rc; hwirq = opal_xive_allocate_irq_raw(chipid); if (hwirq < 0) return -ENOENT; rc = opal_xive_get_irq_info(hwirq, &flags, NULL, &trigger_page, NULL, NULL); if (rc || !trigger_page) { xive_native_free_irq(hwirq); return -ENOENT; } *irq = hwirq; *trigger_addr = be64_to_cpu(trigger_page); return 0; } We can have common function for VAS and cxl except per chip IRQ allocation is needed for each VAS instance. I will post patch-set with this change. Thanks Haren