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[14.202.190.183]) by smtp.gmail.com with ESMTPSA id m9sm7983068pff.93.2020.03.22.17.24.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 22 Mar 2020 17:24:24 -0700 (PDT) Date: Mon, 23 Mar 2020 10:20:54 +1000 From: Nicholas Piggin Subject: Re: [PATCH v8 01/14] powerpc/xive: Define xive_native_alloc_irq_on_chip() To: Haren Myneni , mpe@ellerman.id.au References: <1584598120.9256.15237.camel@hbabu-laptop> <1584598352.9256.15242.camel@hbabu-laptop> In-Reply-To: <1584598352.9256.15242.camel@hbabu-laptop> MIME-Version: 1.0 User-Agent: astroid/0.15.0 (https://github.com/astroidmail/astroid) Message-Id: <1584922512.kzufg0h76s.astroid@bobo.none> Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mikey@neuling.org, ajd@linux.ibm.com, hch@infradead.org, oohall@gmail.com, =?iso-8859-1?q?C=E9dric?= Le Goater , sukadev@linux.vnet.ibm.com, linuxppc-dev@lists.ozlabs.org, herbert@gondor.apana.org.au Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" Haren Myneni's on March 19, 2020 4:12 pm: >=20 > This function allocates IRQ on a specific chip. VAS needs per chip > IRQ allocation and will have IRQ handler per VAS instance. Can't see a problem, but don't really know the XIVE code. C=C3=A9dric seems= =20 like an obvious omission from CC here. Thanks, Nick >=20 > Signed-off-by: Haren Myneni > --- > arch/powerpc/include/asm/xive.h | 9 ++++++++- > arch/powerpc/sysdev/xive/native.c | 6 +++--- > 2 files changed, 11 insertions(+), 4 deletions(-) >=20 > diff --git a/arch/powerpc/include/asm/xive.h b/arch/powerpc/include/asm/x= ive.h > index 93f982db..d08ea11 100644 > --- a/arch/powerpc/include/asm/xive.h > +++ b/arch/powerpc/include/asm/xive.h > @@ -5,6 +5,8 @@ > #ifndef _ASM_POWERPC_XIVE_H > #define _ASM_POWERPC_XIVE_H > =20 > +#include > + > #define XIVE_INVALID_VP 0xffffffff > =20 > #ifdef CONFIG_PPC_XIVE > @@ -108,7 +110,6 @@ struct xive_q { > int xive_native_populate_irq_data(u32 hw_irq, > struct xive_irq_data *data); > void xive_cleanup_irq_data(struct xive_irq_data *xd); > -u32 xive_native_alloc_irq(void); > void xive_native_free_irq(u32 irq); > int xive_native_configure_irq(u32 hw_irq, u32 target, u8 prio, u32 sw_ir= q); > =20 > @@ -137,6 +138,12 @@ int xive_native_set_queue_state(u32 vp_id, uint32_t = prio, u32 qtoggle, > u32 qindex); > int xive_native_get_vp_state(u32 vp_id, u64 *out_state); > bool xive_native_has_queue_state_support(void); > +extern u32 xive_native_alloc_irq_on_chip(u32 chip_id); > + > +static inline u32 xive_native_alloc_irq(void) > +{ > + return xive_native_alloc_irq_on_chip(OPAL_XIVE_ANY_CHIP); > +} > =20 > #else > =20 > diff --git a/arch/powerpc/sysdev/xive/native.c b/arch/powerpc/sysdev/xive= /native.c > index 0ff6b73..14d4406 100644 > --- a/arch/powerpc/sysdev/xive/native.c > +++ b/arch/powerpc/sysdev/xive/native.c > @@ -279,12 +279,12 @@ static int xive_native_get_ipi(unsigned int cpu, st= ruct xive_cpu *xc) > } > #endif /* CONFIG_SMP */ > =20 > -u32 xive_native_alloc_irq(void) > +u32 xive_native_alloc_irq_on_chip(u32 chip_id) > { > s64 rc; > =20 > for (;;) { > - rc =3D opal_xive_allocate_irq(OPAL_XIVE_ANY_CHIP); > + rc =3D opal_xive_allocate_irq(chip_id); > if (rc !=3D OPAL_BUSY) > break; > msleep(OPAL_BUSY_DELAY_MS); > @@ -293,7 +293,7 @@ u32 xive_native_alloc_irq(void) > return 0; > return rc; > } > -EXPORT_SYMBOL_GPL(xive_native_alloc_irq); > +EXPORT_SYMBOL_GPL(xive_native_alloc_irq_on_chip); > =20 > void xive_native_free_irq(u32 irq) > { > --=20 > 1.8.3.1 >=20 >=20 >=20 >=20 =