From: Nicholas Piggin <npiggin@gmail.com>
To: Jordan Niethe <jniethe5@gmail.com>, linuxppc-dev@lists.ozlabs.org
Cc: alistair@popple.id.au, dja@axtens.net, bala24@linux.ibm.com
Subject: Re: [PATCH v4 13/16] powerpc: Support prefixed instructions in alignment handler
Date: Mon, 23 Mar 2020 17:05:42 +1000 [thread overview]
Message-ID: <1584947091.jsvdec8of0.astroid@bobo.none> (raw)
In-Reply-To: <20200320051809.24332-14-jniethe5@gmail.com>
Jordan Niethe's on March 20, 2020 3:18 pm:
> Alignment interrupts can be caused by prefixed instructions accessing
> memory. Prefixed instructions are not permitted to cross 64-byte
> boundaries. If they do the alignment interrupt is invoked with SRR1
> BOUNDARY bit set. If this occurs send a SIGBUS to the offending process
> if in user mode. If in kernel mode call bad_page_fault().
>
> Signed-off-by: Jordan Niethe <jniethe5@gmail.com>
> ---
> v2: - Move __get_user_instr() and __get_user_instr_inatomic() to this
> commit (previously in "powerpc sstep: Prepare to support prefixed
> instructions").
> - Rename sufx to suffix
> - Use a macro for calculating instruction length
> v3: Move __get_user_{instr(), instr_inatomic()} up with the other
> get_user definitions and remove nested if.
> v4: Just do the things for alignment_exception(). Other changes handled
> elsewhere.
> ---
> arch/powerpc/kernel/traps.c | 21 ++++++++++++++++++++-
> 1 file changed, 20 insertions(+), 1 deletion(-)
>
> diff --git a/arch/powerpc/kernel/traps.c b/arch/powerpc/kernel/traps.c
> index a4764b039749..cd8b3043c268 100644
> --- a/arch/powerpc/kernel/traps.c
> +++ b/arch/powerpc/kernel/traps.c
> @@ -583,6 +583,10 @@ static inline int check_io_access(struct pt_regs *regs)
> #define REASON_ILLEGAL (ESR_PIL | ESR_PUO)
> #define REASON_PRIVILEGED ESR_PPR
> #define REASON_TRAP ESR_PTR
> +#define REASON_PREFIXED 0
> +#define REASON_BOUNDARY 0
> +
> +#define inst_length(reason) 4
>
> /* single-step stuff */
> #define single_stepping(regs) (current->thread.debug.dbcr0 & DBCR0_IC)
> @@ -597,6 +601,10 @@ static inline int check_io_access(struct pt_regs *regs)
> #define REASON_ILLEGAL SRR1_PROGILL
> #define REASON_PRIVILEGED SRR1_PROGPRIV
> #define REASON_TRAP SRR1_PROGTRAP
> +#define REASON_PREFIXED SRR1_PREFIXED
> +#define REASON_BOUNDARY SRR1_BOUNDARY
> +
> +#define inst_length(reason) (((reason) & REASON_PREFIXED) ? 8 : 4)
Looks good. If you define REASON_BOUNDARY 0, then this will constant
fold away so no need to define it twice.
Thanks,
Nick
next prev parent reply other threads:[~2020-03-23 7:12 UTC|newest]
Thread overview: 65+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-20 5:17 [PATCH v4 00/16] Initial Prefixed Instruction support Jordan Niethe
2020-03-20 5:17 ` [PATCH v4 01/16] powerpc/xmon: Remove store_inst() for patch_instruction() Jordan Niethe
2020-03-23 6:19 ` Nicholas Piggin
2020-03-20 5:17 ` [PATCH v4 02/16] xmon: Move out-of-line instructions to text section Jordan Niethe
2020-03-23 5:59 ` Balamuruhan S
2020-03-23 6:05 ` Balamuruhan S
2020-03-23 9:26 ` Jordan Niethe
2020-03-23 6:22 ` Nicholas Piggin
2020-03-20 5:17 ` [PATCH v4 03/16] powerpc: Use a datatype for instructions Jordan Niethe
2020-03-23 6:07 ` Balamuruhan S
2020-03-23 6:23 ` Nicholas Piggin
2020-03-23 9:28 ` Jordan Niethe
2020-03-23 9:51 ` Nicholas Piggin
2020-03-24 2:58 ` Michael Ellerman
2020-03-24 3:21 ` Jordan Niethe
2020-04-01 10:32 ` Balamuruhan S
2020-04-01 23:52 ` Jordan Niethe
2020-04-02 23:44 ` Alistair Popple
2020-04-03 0:09 ` Jordan Niethe
2020-03-20 5:17 ` [PATCH v4 04/16] powerpc: Use a macro for creating instructions from u32s Jordan Niethe
2020-03-23 6:26 ` Nicholas Piggin
2020-03-23 9:29 ` Jordan Niethe
2020-03-20 5:17 ` [PATCH v4 05/16] powerpc: Use a function for masking instructions Jordan Niethe
2020-03-23 6:37 ` Nicholas Piggin
2020-03-23 9:31 ` Jordan Niethe
2020-03-20 5:17 ` [PATCH v4 06/16] powerpc: Use a function for getting the instruction op code Jordan Niethe
2020-03-23 6:54 ` Balamuruhan S
2020-03-23 9:35 ` Jordan Niethe
2020-03-20 5:18 ` [PATCH v4 07/16] powerpc: Introduce functions for instruction nullity and equality Jordan Niethe
2020-03-23 6:43 ` Nicholas Piggin
2020-03-23 9:31 ` Jordan Niethe
2020-03-20 5:18 ` [PATCH v4 08/16] powerpc: Use an accessor for word instructions Jordan Niethe
2020-03-23 11:12 ` Balamuruhan S
2020-03-24 3:18 ` Jordan Niethe
2020-03-24 6:22 ` Balamuruhan S
2020-03-20 5:18 ` [PATCH v4 09/16] powerpc: Use a function for reading instructions Jordan Niethe
2020-03-23 8:00 ` Nicholas Piggin
2020-03-23 8:43 ` Balamuruhan S
2020-03-23 10:09 ` Jordan Niethe
2020-03-23 10:36 ` Nicholas Piggin
2020-03-20 5:18 ` [PATCH v4 10/16] powerpc: Make test_translate_branch() independent of instruction length Jordan Niethe
2020-03-20 5:18 ` [PATCH v4 11/16] powerpc: Enable Prefixed Instructions Jordan Niethe
2020-03-23 7:02 ` Nicholas Piggin
2020-03-20 5:18 ` [PATCH v4 12/16] powerpc: Define new SRR1 bits for a future ISA version Jordan Niethe
2020-03-23 7:03 ` Nicholas Piggin
2020-03-20 5:18 ` [PATCH v4 13/16] powerpc: Support prefixed instructions in alignment handler Jordan Niethe
2020-03-23 7:05 ` Nicholas Piggin [this message]
2020-03-23 9:35 ` Jordan Niethe
2020-03-20 5:18 ` [PATCH v4 14/16] powerpc64: Add prefixed instructions to instruction data type Jordan Niethe
2020-03-23 6:58 ` Nicholas Piggin
2020-03-23 7:33 ` Nicholas Piggin
2020-03-23 23:45 ` Jordan Niethe
2020-03-24 5:40 ` Nicholas Piggin
2020-03-30 9:05 ` Alistair Popple
2020-03-30 9:13 ` Jordan Niethe
2020-03-20 5:18 ` [PATCH v4 15/16] powerpc sstep: Add support for prefixed load/stores Jordan Niethe
2020-03-23 8:54 ` Balamuruhan S
2020-03-20 5:18 ` [PATCH v4 16/16] powerpc sstep: Add support for prefixed fixed-point arithmetic Jordan Niethe
2020-03-23 10:05 ` Balamuruhan S
2020-03-23 6:18 ` [PATCH v4 00/16] Initial Prefixed Instruction support Nicholas Piggin
2020-03-23 9:25 ` Jordan Niethe
2020-03-23 10:17 ` Nicholas Piggin
2020-03-24 2:54 ` Jordan Niethe
2020-03-24 2:59 ` Jordan Niethe
2020-03-24 5:44 ` Nicholas Piggin
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